Research Article Open Access

Low Power Hardware Implementation of High Speed FFT Core

M. Kannan1 and S. K. Srivatsa1
  • 1 ,
Journal of Computer Science
Volume 3 No. 6, 2007, 376-382

DOI: https://doi.org/10.3844/jcssp.2007.376.382

Submitted On: 10 June 2006 Published On: 30 June 2007

How to Cite: Kannan, M. & Srivatsa, S. K. (2007). Low Power Hardware Implementation of High Speed FFT Core. Journal of Computer Science, 3(6), 376-382. https://doi.org/10.3844/jcssp.2007.376.382

Abstract

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift and addition operations to realize complex multiplications.

  • 1,433 Views
  • 1,806 Downloads
  • 4 Citations

Download

Keywords

  • Dual port RAM
  • shift register
  • finite state machine