TY  - JOUR
AU  - Kannan, M. 
AU  - Srivatsa, S. K. 
PY  - 2007
TI  - Low Power Hardware Implementation of High Speed FFT Core
JF  - Journal of Computer Science
VL  - 3
IS  - 6
DO  - 10.3844/jcssp.2007.376.382
UR  - https://thescipub.com/abstract/jcssp.2007.376.382
AB  - Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift and addition operations to realize complex multiplications.