@article {10.3844/jcssp.2007.376.382, article_type = {journal}, title = {Low Power Hardware Implementation of High Speed FFT Core}, author = {Kannan, M. and Srivatsa, S. K.}, volume = {3}, number = {6}, year = {2007}, month = {Jun}, pages = {376-382}, doi = {10.3844/jcssp.2007.376.382}, url = {https://thescipub.com/abstract/jcssp.2007.376.382}, abstract = {Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift and addition operations to realize complex multiplications.}, journal = {Journal of Computer Science}, publisher = {Science Publications} }