Low Power Hardware Implementation of High Speed FFT Core
M. Kannan and S. K. Srivatsa
DOI : 10.3844/jcssp.2007.376.382
Journal of Computer Science
Volume 3, Issue 6
Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift and addition operations to realize complex multiplications.
© 2007 M. Kannan and S. K. Srivatsa. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.