Gate Replacement Technique for Reducing Leakage Current in Wallace Tree Multiplier

Abstract

Leakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace tree multiplier architecture which has been designed by using one bit full adders. This technique replaces the gate which is at worst leakage state by a library gate .In this technique the actual output logic state is maintained in active mode. The main objective of our study is to calculate leakage power in 4×4 Wallace tree multiplier by applied gate replacement technique and it is compared with 4×4 Wallace tree full adder multiplier. The proposed method reduces 43% of leakage power in 4×4 Wallace tree multiplier.