Research Article Open Access

High Performance and Low Leakage 3DSOI Fin-FET SRAM

D. Sudha1, Ch. Santhirani2 and Sreenivasa Rao Ijjada3
  • 1 A.N University, India
  • 2 GITAM University, India
  • 3 DMSSSVH College of Engineering, India
American Journal of Engineering and Applied Sciences
Volume 10 No. 1, 2017, 101-107

DOI: https://doi.org/10.3844/ajeassp.2017.101.107

Submitted On: 1 October 2016 Published On: 9 February 2017

How to Cite: Sudha, D., Santhirani, C. & Ijjada, S. R. (2017). High Performance and Low Leakage 3DSOI Fin-FET SRAM. American Journal of Engineering and Applied Sciences, 10(1), 101-107. https://doi.org/10.3844/ajeassp.2017.101.107

Abstract

In recent semiconductor designs, the major key factors: Competent device simulations, precise device characterization, well power optimization, new architectural design and cost-effective fabrication drives the designers attention towards multi gate transistors as an alternative to MOSFET. Non planner device structures are a competitive edge over planner devices. Silicon-on-Insulator (SOI) FinFETs are hopeful among variety of multi-gate structures as they have simple fabrication, Superior gate control, lower subthreshold leakage and minimized susceptibility to process variations. Low leakage memory cells play a significant role of power consumption in the recent VLSI Systems. In this study, Ultra-low Voltage Asymmetric Short Gate (UVASG) FinFET is modeled with TCAD tools for low leakages and FinFET based SRAM has been proposed as a substitute for the bulk devices.

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Keywords

  • Non Planner Devices
  • SOI
  • Ultra Low Voltage
  • FINFET
  • TCAD
  • SRAM