@article {10.3844/ajeassp.2017.101.107,
article_type = {journal},
title = {High Performance and Low Leakage 3DSOI Fin-FET SRAM},
author = {Sudha, D. and Santhirani, Ch. and Ijjada, Sreenivasa Rao},
volume = {10},
number = {1},
year = {2017},
month = {Feb},
pages = {101-107},
doi = {10.3844/ajeassp.2017.101.107},
url = {https://thescipub.com/abstract/ajeassp.2017.101.107},
abstract = {In recent semiconductor designs, the major key factors: Competent device simulations, precise device characterization, well power optimization, new architectural design and cost-effective fabrication drives the designers attention towards multi gate transistors as an alternative to MOSFET. Non planner device structures are a competitive edge over planner devices. Silicon-on-Insulator (SOI) FinFETs are hopeful among variety of multi-gate structures as they have simple fabrication, Superior gate control, lower subthreshold leakage and minimized susceptibility to process variations. Low leakage memory cells play a significant role of power consumption in the recent VLSI Systems. In this study, Ultra-low Voltage Asymmetric Short Gate (UVASG) FinFET is modeled with TCAD tools for low leakages and FinFET based SRAM has been proposed as a substitute for the bulk devices.},
journal = {American Journal of Engineering and Applied Sciences},
publisher = {Science Publications}
}