Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee
- 1 , Afganistan
- 2 ,
Copyright: © 2020 Nesreen Mahmoud Hammam Ismail and Masuri Othman. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it is meant to be a low cost communication system. Phase Locked Loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD used only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz-1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA, lock-in time is 27 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.
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- Phase frequency detector
- charge pump
- voltage controlled oscillator and dual modulus