Research Article Open Access

Design of a High-Performance IP Switching Architecture

Hattab Guesmi, Belgacem Bouallegue, Ridha Djemal and Rached Tourki

Abstract

In this study we present the architecture for use in high-performance switching networks with support quality of service (QoS) guarantees. Quality of services guarantees in terms of delay, through-put and loss rate can be provided by using mechanism's support like scheduling and buffer management at switching architecture in packet switching networks. Our architecture is based on a new data structure for the scheduling and memories management which is the circular linked list and the pipeline for the active queues elements. In addition to being very fast, the architecture also scales very well to a large number of priority levels and to large queue size. We give a detailed description of the block that support QoS guarantees. However our proposed architecture is composed of three parts: input controller, backplane and output controller. And we give the corresponding algorithms and the corresponding implementation of this architecture.

Journal of Computer Science
Volume 2 No. 3, 2006, 218-223

DOI: https://doi.org/10.3844/jcssp.2006.218.223

Submitted On: 7 October 2005 Published On: 31 March 2006

How to Cite: Guesmi, H., Bouallegue, B., Djemal, R. & Tourki, R. (2006). Design of a High-Performance IP Switching Architecture. Journal of Computer Science, 2(3), 218-223. https://doi.org/10.3844/jcssp.2006.218.223

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Keywords

  • IP switching architecture
  • high-performance
  • switching networks