Fabrication of Single Layer SiO2 and Si3N4 as Antireflection Coating on Silicon Solar Cell Using Silvaco Software
A. Lennie, H. Abdullah, S. Shaari and K. Sopian
DOI : 10.3844/ajassp.2009.2043.2049
American Journal of Applied Sciences
Volume 6, Issue 12
The main objectives was to investigate and enhance the short circuit current density, Jsc and also to improve the efficiency of silicon solar cell by fabricating a layer of silicon dioxide (SiO2) and silicon nitride (Si3N4) coatings on silicon solar cell. This fabrication carried out on high temperature during annealing process from 800-1050°C and variable thickness of antireflection coating (ARC) layer from 50-90 nm thick. The photovoltaic properties of Si3N4 layer have been compared with SiO2 layer to determine which material is suitable in fabricating single layer ARC. Solar cell simulation could be useful for time saving and cost consumption. Problem statement: The Silvaco software is not widely used in designing the 2D solar cell devices because there are lots of 1D, 2D and 3Dsimulation beside Silvaco software such as MicroTec, SCAPS-1D. Approach: The silicon dioxide (SiO2) and silicon nitride (Si3N4) coating have been modeled and fabricated on silicon solar cell by using Silvaco software packaging. Results: For SiO2 results, the FF value is approximately 0.758 and η maximum 9.43%. In annealing process, the temperature becomes higher resulted increasing of pn junction depth. However, not to Voc and Jsc values, both parameters were slowly decreased when temperature increased. Meanwhile, when the thickness of SiO2 layer is increased, the parameters of pn junction depth, Jsc, Voc, FF and η were decreased slowly. As for Si3N4 result, the calculated FF approximately 0.758 and h maximum is 9.57%. During annealing process, the temperature increasing constantly follows the increasing of pn junction depth and Jsc, meanwhile the Voc is decreased slowly. In variable Si3N4 thickness simulation, the output parameters of pn junction depth, Jsc, Voc, FF and η were decreased when the thickness increased 10 nm each simulation. Conclusion: The optimum temperature during annealing process for SiO2 is 950°C, while for Si3N4 is 1050°C. For the thickness analysis, the optimum ARC thickness for SiO2 and Si3N4 layer is 50 nm both.
© 2009 A. Lennie, H. Abdullah, S. Shaari and K. Sopian. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.