Research Article Open Access

Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System

P. Nirmal Kumar1, S. Anandhi2, M. Elancheralathan2 and J. Raja Paul Perinbam1
  • 1 , Afganistan
  • 2 ,
Journal of Computer Science
Volume 3 No. 12, 2007, 934-938

DOI: https://doi.org/10.3844/jcssp.2007.934.938

Submitted On: 2 February 2008 Published On: 31 December 2007

How to Cite: Kumar, P. N., Anandhi, S., Elancheralathan, M. & Perinbam, J. R. P. (2007). Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System. Journal of Computer Science, 3(12), 934-938. https://doi.org/10.3844/jcssp.2007.934.938

Abstract

This research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails as open (iii) sensors fails as short circuit. The objective of this research is to test the desired optimal circuits evolved by decoding the configuration bit streams. The logic simulation tool used to perform fault simulation is AUSIM (Auburn University Simulator).

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Keywords

  • FPGA
  • Virtual Reconfigurable Circuit (VRC)
  • fault tolerant system
  • sensor failure
  • AUSIM
  • ASL