TY - JOUR AU - Kumar, P. Nirmal AU - Anandhi, S. AU - Elancheralathan, M. AU - Perinbam, J. Raja Paul PY - 2007 TI - Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System JF - Journal of Computer Science VL - 3 IS - 12 DO - 10.3844/jcssp.2007.934.938 UR - https://thescipub.com/abstract/jcssp.2007.934.938 AB - This research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails as open (iii) sensors fails as short circuit. The objective of this research is to test the desired optimal circuits evolved by decoding the configuration bit streams. The logic simulation tool used to perform fault simulation is AUSIM (Auburn University Simulator).