Research Article Open Access

Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

Somayeh Timarchi1, Omid Kavehei1 and Keivan Navi1
  • 1 ,
American Journal of Applied Sciences
Volume 5 No. 4, 2008, 312-319

DOI: https://doi.org/10.3844/ajassp.2008.312.319

Submitted On: 27 July 2007 Published On: 30 April 2008

How to Cite: Timarchi, S., Kavehei, O. & Navi, K. (2008). Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System. American Journal of Applied Sciences, 5(4), 312-319. https://doi.org/10.3844/ajassp.2008.312.319

Abstract

Modulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and delay.

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Keywords

  • Modulo 2n+1 addition
  • carry save diminished-one number system
  • parallel-prefix adders
  • residue number system
  • computer arithmetic
  • VLSI circuits