Research Article Open Access

Design of a LOW Cost IC Tester

Liakot Ali1, Roslina Sidek1, Ishak Aris1, Mohd. Alauddin Mohd. Ali1 and Bambang Sunaryo Suparjo1
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American Journal of Applied Sciences
Volume 2 No. 4, 2005, 824-827

DOI: https://doi.org/10.3844/ajassp.2005.824.827

Submitted On: 3 November 2005 Published On: 30 April 2005

How to Cite: Ali, L., Sidek, R., Aris, I., Ali, M. A. M. & Suparjo, B. S. (2005). Design of a LOW Cost IC Tester. American Journal of Applied Sciences, 2(4), 824-827. https://doi.org/10.3844/ajassp.2005.824.827

Abstract

Low cost Integrated Circuit (IC) testing is now a burning issue in semiconductor technology. Conventional IC tester, Automatic Test Equipment (ATE), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach of IC testing has been emerged as an economically viable alternative to the expensive deterministic testing approach. This study introduces the design of a System-on-a-chip (Soc) implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-port facilities efficiently. It can also be used for testing Printed Circuit Board (PCB) interconnection faults.

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Keywords

  • ATE
  • seed
  • LFSR
  • SoC