TY  - JOUR
AU  - Ali, Liakot 
AU  - Sidek, Roslina 
AU  - Aris, Ishak 
AU  - Ali, Mohd. Alauddin Mohd. 
AU  - Suparjo, Bambang Sunaryo 
PY  - 2005
TI  - Design of a LOW Cost IC Tester
JF  - American Journal of Applied Sciences
VL  - 2
IS  - 4
DO  - 10.3844/ajassp.2005.824.827
UR  - https://thescipub.com/abstract/ajassp.2005.824.827
AB  - Low cost Integrated Circuit (IC) testing is now a burning issue in semiconductor technology. Conventional IC tester, Automatic Test Equipment (ATE), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach of IC testing has been emerged as an economically viable alternative to the expensive deterministic testing approach. This study introduces the design of a System-on-a-chip (Soc) implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-port facilities efficiently. It can also be used for testing Printed Circuit Board (PCB) interconnection faults.