Journal of Computer Science

Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL

Hasan Krad and Aws Y. Al-Taie

DOI : 10.3844/jcssp.2008.305.308

Journal of Computer Science

Volume 4, Issue 4

Pages 305-308

Abstract

This study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study's main focus is on the speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a better performance over the multiplier with a ripple adder in terms of gate delays. Under the worst case, the multiplier with the fast adder shows approximately twice the speed of the multiplier with the ripple adder. The multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carry-look-ahead adder uses time = 659.292 ns.

Copyright

© 2008 Hasan Krad and Aws Y. Al-Taie. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.