Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System
P. Nirmal Kumar, S. Anandhi, M. Elancheralathan and J. Raja Paul Perinbam
DOI : 10.3844/jcssp.2007.934.938
Journal of Computer Science
Volume 3, Issue 12
This research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails as open (iii) sensors fails as short circuit. The objective of this research is to test the desired optimal circuits evolved by decoding the configuration bit streams. The logic simulation tool used to perform fault simulation is AUSIM (Auburn University Simulator).
© 2007 P. Nirmal Kumar, S. Anandhi, M. Elancheralathan and J. Raja Paul Perinbam. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.