An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
Abdellatif Mtibaa, Abdessalem B. Abdelali, Lotfi Boussaid and Elbey Bourennane
DOI : 10.3844/jcssp.2006.422.430
Journal of Computer Science
Volume 2, Issue 5
In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) for each task. We study the effect of hardware resources limitation in the choice of the algorithm implementation design point. The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints.
© 2006 Abdellatif Mtibaa, Abdessalem B. Abdelali, Lotfi Boussaid and Elbey Bourennane. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.