TY  - JOUR
AU  - Mtibaa, Abdellatif 
AU  - Abdelali, Abdessalem B. 
AU  - Boussaid, Lotfi 
AU  - Bourennane, Elbey 
PY  - 2006
TI  - An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware
JF  - Journal of Computer Science
VL  - 2
IS  - 5
DO  - 10.3844/jcssp.2006.422.430
UR  - https://thescipub.com/abstract/jcssp.2006.422.430
AB  - In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) for each task. We study the effect of hardware resources limitation in the choice of the algorithm implementation design point. The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints.