A Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance Scheme
Uma Ramadass, Krishnappriya, Jebashini Ponnian and P. Dhavachelvan
DOI : 10.3844/ajassp.2013.881.892
American Journal of Applied Sciences
Volume 10, Issue 8
In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the interconnect delay estimates can be improved by deploying the conductance effect. The simulation results shows the proposed interconnect scheme performance is better than the existing in terms of delay, power and the figure of merit. The performance analysis depicts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.
© 2013 Uma Ramadass, Krishnappriya, Jebashini Ponnian and P. Dhavachelvan. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.