American Journal of Applied Sciences

Design of a LOW Cost IC Tester

Liakot Ali, Roslina Sidek, Ishak Aris, Mohd. Alauddin Mohd. Ali and Bambang Sunaryo Suparjo

DOI : 10.3844/ajassp.2005.824.827

American Journal of Applied Sciences

Volume 2, Issue 4

Pages 824-827

Abstract

Low cost Integrated Circuit (IC) testing is now a burning issue in semiconductor technology. Conventional IC tester, Automatic Test Equipment (ATE), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach of IC testing has been emerged as an economically viable alternative to the expensive deterministic testing approach. This study introduces the design of a System-on-a-chip (Soc) implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-port facilities efficiently. It can also be used for testing Printed Circuit Board (PCB) interconnection faults.

Copyright

© 2005 Liakot Ali, Roslina Sidek, Ishak Aris, Mohd. Alauddin Mohd. Ali and Bambang Sunaryo Suparjo. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.