TY  - JOUR
AU  - Bobbala, Lakshmi Deepika 
AU  - Debnath, Monobrata 
AU  - Lee, Byeong Kil 
PY  - 2011
TI  - Composite Pseudo Associative Cache with Victim Cache for Mobile Processors
JF  - Journal of Computer Science
VL  - 7
IS  - 10
DO  - 10.3844/jcssp.2011.1448.1457
UR  - https://thescipub.com/abstract/jcssp.2011.1448.1457
AB  - Problem statement: Multi-core trends are becoming dominant, creating sophisticated and complicated cache structures. One of the easiest ways to design cache memory for increasing performance is to double the cache size. The big cache size is directly related to the area and power consumption. Especially in mobile processors, simple increase of the cache size may significantly affect its chip area and power. Without increasing the size of the cache, we propose a novel method to improve the overall performance. Approach: We proposed a composite cache mechanism for 1 and L2 cache to maximize cache performance within a given cache size. This technique could be used without increasing cache size and set associatively by emphasizing primary way utilization and pseudo-associatively. We also added victim cache to composite pseudo associative cache for further improvement. Results: Based on our experiments with the sampled SPEC CPU2006 workload, the proposed cache mechanism showed the remarkable reduction in cache misses without affecting the size. Conclusion/Recommendation: The variation of performance improvement depends on benchmark, cache size and set associatively, but the proposed scheme shows more sensitivity to cache size increase than set associatively increase.