TY  - JOUR
AU  - Krad, Hasan 
AU  - Al-Taie, Aws Y. 
PY  - 2008
TI  - Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL 
JF  - Journal of Computer Science
VL  - 4
IS  - 4
DO  - 10.3844/jcssp.2008.305.308
UR  - https://thescipub.com/abstract/jcssp.2008.305.308
AB  - This study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study's main focus is on the speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a better performance over the multiplier with a ripple adder in terms of gate delays. Under the worst case, the multiplier with the fast adder shows approximately twice the speed of the multiplier with the ripple adder. The multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carry-look-ahead adder uses time = 659.292 ns.