TY  - JOUR
AU  - Algnabi, Yazan Samir 
AU  - Teymourzadeh, Rozita 
AU  - Othman, Masuri 
AU  - Islam, Md Shabiul 
AU  - Hong, Mok Vee 
PY  - 2010
TI  - On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture
JF  - American Journal of Engineering and Applied Sciences
VL  - 3
IS  - 4
DO  - 10.3844/ajeassp.2010.757.764
UR  - https://thescipub.com/abstract/ajeassp.2010.757.764
AB  - Problem statement: The need for wireless communication has driven the communication
systems to high performance. However, the main bottleneck that affects the communication capability
is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study
presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure.
The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplierless
single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT)
FFT structure. The proposed design focused on the trade-off between the speed and active silicon area
for the chip implementation. The new architecture was investigated and simulated with MATLAB
software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly
functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto
board was used to implement and test the design on the real hardware. Results: As a result, from the
findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total
equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly.
In comparison with the conventional butterfly architecture, design that can only run at a maximum
clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock
frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock
frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier.
Conclusion: It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less
butterfly for FFT structure is an enabler in solving problems that affect communications capability in
FFT and possesses huge potentials for future related works and research areas.