Research Article Open Access

A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS

Bakoune Pierre Hypolite1, Wembe Tafo Evariste1 and Moukengue Imano Adolphe1
  • 1 University of Douala, Cameroon
American Journal of Engineering and Applied Sciences
Volume 12 No. 2, 2019, 156-165

DOI: https://doi.org/10.3844/ajeassp.2019.156.165

Submitted On: 20 October 2018 Published On: 6 May 2019

How to Cite: Hypolite, B. P., Evariste, W. T. & Adolphe, M. I. (2019). A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS. American Journal of Engineering and Applied Sciences, 12(2), 156-165. https://doi.org/10.3844/ajeassp.2019.156.165

Abstract

This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GHZ. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.

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Keywords

  • Dynamic
  • 90 nm PTM CMOS
  • Analog to Digital Converter (ADC)
  • Double Tail Structure Positive Feedback