Research Article Open Access

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

Hedi Abdelkrim1, Slim Ben Othman1, Ahmed Karim Ben Salem1 and Slim Ben Saoud1
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American Journal of Engineering and Applied Sciences
Volume 5 No. 1, 2012, 15-24

DOI: https://doi.org/10.3844/ajeassp.2012.15.24

Submitted On: 28 December 2011 Published On: 18 February 2012

How to Cite: Abdelkrim, H., Othman, S. B., Salem, A. K. B. & Saoud, S. B. (2012). Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation . American Journal of Engineering and Applied Sciences, 5(1), 15-24. https://doi.org/10.3844/ajeassp.2012.15.24

Abstract

Problem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using Multiprocessor SoC (MPSoC) architecture. In order to enhance flexibility and performance of the considered system, we design different modules of HW current controller of electronic motor. A Dynamic Partial Reconfiguration (DPR) mechanism allowing switching on the fly between those modules is described. Results: Test and validation are done to validate the approach adopted. Experimental results confirmed the efficiency of the approach and allow us to determine more recommendations that should be considered while designing a RSoC control drive system. Conclusion/Recommendations: DPR enable flexible control system hardware design. This concept allows switching between different low order controls.

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Keywords

  • Motor drive
  • dynamic partial reonfiguration
  • MPSoC
  • FPGA
  • RSoC