Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers
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Copyright: © 2020 Muhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar and Fahad K. Al-Hussein. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Problem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. Approach: This study presented the design and implementation of basic building blocks used in power-efficient Baugh-Wooley multipliers using FPGA Spartan-3AN device. The implementation of power-efficient Baugh-Wooley multipliers is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The design and implementation of basic building blocks of power-efficient Baugh-Wooley multipliers showed reasonable FPGA resource utilization, which is an indication that rest of the available resources could be utilized for other embedded resources. Conclusion: The Spartan-3AN FPGA device could be used at this stage of basic building blocks reasonably.
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- Baugh-Wooley algorithm
- Digital Signal Processing (DSP)
- Field Programmable Gate Array (FPGA)
- fixed-width multiplier