A Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection Ratio
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Copyright: © 2020 Ismail Nabhan and Moussa Abdallah. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Problem statement: High speed operational amplifier is always an on-going research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0.5 μm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure stability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain, a 24 V μS-1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMOS operational amplifier in Jordan as the authors are aware, is well-suited to low-voltage applications since it does not require cascade output stages.
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- operational amplifier
- slew rate