Research Article Open Access

Hardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification System

Jahariah Sampe1 and Masuri Othman1
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American Journal of Engineering and Applied Sciences
Volume 1 No. 2, 2008, 136-140

DOI: https://doi.org/10.3844/ajeassp.2008.136.140

Submitted On: 5 March 2008 Published On: 30 June 2008

How to Cite: Sampe, J. & Othman, M. (2008). Hardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification System . American Journal of Engineering and Applied Sciences, 1(2), 136-140. https://doi.org/10.3844/ajeassp.2008.136.140

Abstract

This paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on its Object Class. Therefore a packet format of the tag consists of an object class bits (OC) and an Identification bits (ID). Meanwhile, the uplink operation is performed a Fast Detection anti-collision technique. This technique is novel in terms of faster identification time by reducing the number of iterations during the identification process. It also reads the ID at once regardless of its length. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx Synthesis Technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer model TLA 5201 for real time verification. From the result, it shows that the proposed HTACA system enables to identify the tags without error at the maximum operating frequency of 180 MHz. As a result, the maximum throughput of this hardware implemented system is 180 Megatags sec-1.

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Keywords

  • Pipeline
  • deterministic
  • downlink and uplink
  • object class
  • real time verification