A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS
Bakoune Pierre Hypolite, Wembe Tafo Evariste and Moukengue Imano Adolphe
DOI : 10.3844/ajeassp.2019.156.165
American Journal of Engineering and Applied Sciences
Volume 12, Issue 2
This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GHZ. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.
© 2019 Bakoune Pierre Hypolite, Wembe Tafo Evariste and Moukengue Imano Adolphe. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.