DFM of Strained-Engineered MOSFETs Using Technology CAD
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Published On: 5 November 2010
Copyright: © 2020 T. K. Maiti and C. K. Maiti. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Problem statement: In this study, a systematic study based on Technology CAD (TCAD) was taken up for the design and Virtual Wafer Fabrication (VWF) of strain-engineered MOSFETs in Si CMOS technology. Approach: A simple manufacturable process recipe was developed to induce uniaxial stress in channel region to obtain enhanced performance in CMOS in 45 nm technology node. Results: Using Synopsys Sentaurus Process simulation tool, high dopant activation and low Transient Enhanced Diffusion (TED) during processing are fully captured. A physics-based mobility model had been developed and implemented in Synopsys Sentaurus Device tool. Sentaurus Device was used to simulate device DC and AC characteristics and also to extract Vth, Ion and Ioff. Conclusion: Optimum process conditions required to meet a set of device specifications had been achieved via the Design of Experiment (DoE) study. Process Compact Model (PCM) was used for performance and manufacturability optimization.
- Technology CAD
- process compact model
- strained-engineered MOSFETs