Research Article Open Access

VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

Rozita Teymourzadeh1, Yazan Samir Algnabi2, Masuri Othman1, Md Shabiul Islam2 and Jimmy Mok Vee Hong2
  • 1 ,
  • 2 , Afganistan
American Journal of Engineering and Applied Sciences
Volume 3 No. 4, 2010, 663-669

DOI: https://doi.org/10.3844/ajeassp.2010.663.669

Submitted On: 4 May 2010
Published On: 5 November 2010

How to Cite: Teymourzadeh, R., Algnabi, Y. S., Othman, M., Islam, M. S. & Hong, J. M. V. (2010). VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers. American Journal of Engineering and Applied Sciences, 3(4), 663-669. https://doi.org/10.3844/ajeassp.2010.663.669

Abstract

Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

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Keywords

  • ASIC
  • CIC
  • CMOS
  • FPGA
  • sigma delta modulator
  • silterra
  • virtex
  • Xilinx