A PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTING

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.


INTRODUCTION
In Very Large Scale Integration (VLSI) design, interconnect delay affects the circuit performance and complexity (Tang et al., 2001). In Deep Submicron and Nanometer design, interconnect has become dominating factor in circuit performance and reliability. Thus the performance of the VLSI circuit is very much depends on wire routing and buffer insertion along the path.
The techniques for interconnect delay such as wire sizing, buffer insertion and buffer sizing are used. Dong et al. (2009) have introduced a heuristic method to solve buffer insertion and wire sizing problem. However, this method did not handle routing with obstacles. Without using any optimization technique or algorithm, the mathematical equation become complexe and number of parameters will be used to solve this routing problem. To solve this complex problem, Particle Swarm Optimization (PSO) is an optimization technique which is an evolutionary computational technique developed (Engelbrecht, 2005). PSO is a robust optimization technique based on movement and intelligent of swarm. Ayob et al. (2010;2012) employed Particle Swarm Optimization (PSO) to solve buffer insertion problem in VLSI routing, with considerations on wire and buffer obstacles.
PSO approach in VLSI routing was first implemented by the authors (Dong et al., 2009). The algorithm was targeting to have shortest path in MRST problem. The problem does not include any buffer and obstacle in VLSI grid graph. The problem is to obtain the optimal path having the minimum value of interconnect delay from source to sink in VLSI using Grid Graph model. The routing path is obtained and then the buffer is inserted to minimize the delay. This technique will have the path with the

JMSS
shortest distance from source to sink whereas the shortest path is considered to have minimum delay. Mahanthi and Rao (2013) have introdued a stochastic based Particle Swarm Optimization algorithm is used to optimize buffer locations to find the shortest path and also simultaneously minimize the congestion.
The objective of this study is to study the impact of pre detective technology model library functions using standard nanometer specifications for efficient routing technique. The particle swarm optimization algorithm is used for optimizing the link between source and sink. The manhattan bending is used for optimizing this algorithm is incorporated. The shortest path routing is established between the source and sink. Buffers are appropriately inserted using PSO algorithm by implementing the shortest path routing in a source to sink. This proposed algorithm is useful for finding the minimum power dissipation of buffers inserted in a VLSI routing. The closed form expression for power dissipation is derived and is simulated with numerical results.
This study is organized as follows. Section II presents the proposed method for inter connect driven routing. Section III analyzes the performance of the proposed model using PSO algorithm. Simulation results are discussed in section IV and section V concludes the study.

Power Dissipation
The interconnect width and spacing are optimized unter two scenarious, 1. Spacing is kept at its minimum value and 2. Spacing is kept the same line width, for various International Technology Roadmap for Semiconductor (ITRS) Technology nodel.
The total capacitance of the wire Equation (1): Where: C g = The gate capacitance C c = The coupling capacitance Equation (2 and 3): Where: t = The interconnect thickness w = The interconnect width h = The dielectric height s = The spacing between the neighbor interconnects The proposed Pre detective Technology Model (PTM) model library functions (http://public.itrs.net/Files/2001ITRS/Home) can be incorporated using nanometer technological specifications to optimize the power. The closed form expression for power dissipation is carried out in this study with buffer as well as without buffer Equation (4): Where: P t = The total power dissipation P w = A without buffer power dissipation P b = A with buffer power dissipation Global interconnects are comprised of wires and buffers. An optimal repeater insertion technique is used to minimize the wire length (shortest path between source to sinks), power dissipation and wire size. This wire size is inversely proportional to the power dissipation and buffer insertion is directly proportional to the power dissipation.

Single Long Uniform Wire Routing Without Buffer Insertion Approach
A single long 45 nm technological node wire interconnects is considered for routing. The gate capacitance C g is kept as 1.92 fF/mm for each segment. The route length is calculated from source to sink represented by segments. The total capacitance is measured with respect to ground for x segments is calculated by 1.92fF×x. The total power is calculated without buffer insertion is Equation (5): Where: V dd = A supply voltage in interconnect driven routing f c = A clock frequency C tg = The total gate capacitance

Single Long Uniform Wire Routing With Buffer Insertion Approach
The buffer is inserted to the Manhattan's bending degrades the power dissipation in the wire interconnect Science Publications JMSS signal. The total buffer insertion is limited to three. The power is dissipated by using wire segments and buffers from source to a sink node Swaminathan et al. (2013), the total power dissipation with buffer insertion is subtracted with the total power dissipation without buffer insertion is calculated and is given by Equation (6): Where: P tnb = The total power without buffer insertion P twb = the total power with buffer insertion Kaur and Sulochanna (2013) the uniform buffer insertion is an efficient technique for driving long interconnects. The objective of a uniform buffer insertion is to minimize the power dissipation and delay a long interconnect.
The total power dissipation with buffer insertion is calculated by Equation (7): Where: n b = The number of buffers b os = The buffer value in one segment The total power dissipation without buffer insertion is represented by Equation (8): The buffer is inserted in an interconnect signal wire connected from a source to a sink node. Hence the power dissipation gets degraded and is calculated.

Two Uniform Wire Routing Without Buffer Insertion Approach
The node wire dimension is assigned as 45 nm. Let S min = W min =102.5 nm. The parameters are taken from the Predictive Technology Model (PTM). The gate capacitances are 7.265 fF/mm and 1.92 fF/mm. V dd = 1V, f c = 15GH Z . The total cross coupling capacitance is calculated by Equation (9): where, C c1 , C c2 , C c3 are the coupling capacitances between two uniform parallel wire in three manhattan bending. C cos is the coupling capacitance in one segment. The total gate capacitance is Equation (10): gt g1 g 2 g3 g 4 g5 g 6 gos where, C g1 , C g2 , C g3 are the gate capacitance in wire one and C g4 , C g5 , C g6 are the gate capacitance value in wire two. The total capacitance is calculated by adding the total coupling capacitance and total gate capacitance. It is calculated by Equation (11): The total Power dissipation in two uniform wire is calculated by Equation (12): The total power dissipation with buffer in Two uniform wire calculated by Equation (13): The total power dissipation in the interconnect signal wires is calculated by Equation (14): Now, the percentage of power saving due to the buffer insertion is calculated by Equation (15) Where: P tw = The total power dissipation without buffer P tb = The total power dissipation with buffer

Delay and Bandwidth Interconnections
The delay of the line segment is optimal. There fore the optimal delay per unit length can be obtained, (Yan et al., 2013;Narasimhan and Sridhar, 2010) Equation (16): The global interconnection total delay D and the number of interconnects N decide the interconnect Science Publications JMSS bandwidth B with the optimal buffer insertion can be definded as (Yan et al., 2013) Equation (17 and 18): Where: C o = The input capacitance C p = The out put capacitance r s = The resistance

Interconnect Driven Routing Using PSO Algorithm
• Initialize each particle with a random velocity and random position • Calculate the cost for each particle • If the current cost is lower than the best value, treat the particle is gBest • Calculate the new velocity and position to each particle • Repeat steps 2-4 until maximum iteration or minimum error criteria is not attained The algorithm is initialized with particles at random positions and then it explores the search space to find better solutions. In every itration, each particle adjusts its velocity to follow two best solutions (Datta et al., 2013) the first is the cognitive part, where the particle follows its own best solution found so far. This is the solution that produces the lowest cost (has the highest fitness). This value is called pbest (particle best) (Yusof et al., 2011;Tang and Mao, 2006). The other best value is the current best solution of the swarm, i.e., the best solution by any particle in the swarm. This value is called gbest (global best) (Kennady and Eberhart, 1995;Eberhart and Shi, 2001).
Each particle adjusts its velocity and position is given by Equation (19 and 20): Where: V = The current velocity V 1 = the new velocity x = The current position X 1 = The new position R 1 and R 1 are distributed random numbers, C 1 and C 2 are acceleration coefficients. C 1 influences the cognitive behavior. i.e., how much the particle will follow its own best solution and C 2 is the factor for social behavior. i.e., how much the particle will follow the swarm's best solution. It has a limited number of parameters and the impact of parameters to the solutions is small compared to other optimization techniques. PSO algorithm determines the sortest path between source to sink. PSO algorithm determine the optimum power that dissipates within the constraint of three manhattan style routing bending with buffer insertion as agreed.

RESULTS
In this section, the power dissipation for various buffers is simulated through MATLAB simulations. The power dissipation is compared with various nanometer technology parameters. Figure 2 and 3 show the power dissipation for number of buffers is simulated in various nanometer technological parameter values for single and two uniform wire routing. Figure 1 shows the power saving for number of buffers is simulated in various nano meter technological parameter value for two uniform wire routing. Figure 2 and 3 is shown that the number of buffers are increased, the power dissipation is also be incresed. It is clearly shown that at 65 nm power dissipation ismore when compared to 32 nm power dissipation. It is seen that for ten buffer insertion, for 32 nm technology model, the power dissipation value is 2×10 11 , but for 65 nm technology model, the power dissipation value is 18×10 11 . It is inferred that the power dissipation is same for both single and two uniform wire routing.

DISCUSSION
The Table 1 and 2 w opt , w opt , s opt , h opt , k opt , τ opt , p opt and B opt are the optimal results with considering the self heating effect and w 1 opt , s 1 opt , h 1 opt , k 1 opt , τ 1 opt , p 1 opt and B 1 opt are the traditional optimization without considering the self heating effect which is from (Tang and Mao, 2006). Figure 1 shows routing. It is shown that the number of buffers are increased, the power saving is also be increased. The power saving is maximum for 32 nm technology model when compared with 45 nm technology model. It is seen that 32 and 65 nm technology models power saving is the same.  The global interconnection power distribution is inversely professional to the width and spacing of the interconnection. which is same as that of the delay. Solower power distribution requires large nterconnection width and spacing. The aim of the global interconnect design is to get a small delay per unit length, low power dissipation and large bandwidth simultaneously unfortunately, it can be seen from the above discussion, small delay and low power dissipation, require large interconnection width and spacing. But large bandwidth requires small interconnection width and spacing (Tep and Yusof, 2010). Table 2 The interconnection less delay, less power dissipation and large bandwidth can be achieved compared to my work. Table 1 shows the optimal wire width w opt , s opt buffer size k opt and the length h opt between two buffers considering the self heating effect is larger than without considering the self heating.

CONCLUSION
The optimal power dissipation for simultaneous buffer insertion and buffer sizing and wire sizing with shortest path constraints using PSO algorithm for VLSI interconnect driven routing has been investigated and analyzed. The closed form expressions for minimizing the total power dissipation using shortest path is calculated. The closed form solutions can be used to efficiently estimate the power dissipation in the stages of the VLSI designs. The simulation results show that the simultaneous buffer insertion/sizing and wiring sizing is better than traditional uniformed buffer insertion in terms of optimal shortest path and optimal power allocation. The self heating effect, the interconnection wire delay, power dissipation and bandwidth, which depend on the interconnect resistance per unit length and capacitance, are analyzed. The proposed optimal model is validated and compared on 90, 65, 40 and 32 nm cmos technology. Performance analysis in this study will facilitate future work on new technology specifications and improved power dissipations and bandwidth and decrese the delay.