Gate Replacement Technique for Reducing Leakage Current in Wallace Tree Multiplier

Leakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace tree multiplier architecture which has been designed by using one bit full adders. This technique replaces the gate which is at worst leakage state by a library gate .In this technique the actual output logic state is maintained in active mode. The main objective of our study is to calculate leakage power in 4×4 Wallace tree multiplier by applied gate replacement technique and it is compared with 4×4 Wallace tree full adder multiplier. The proposed method reduces 43% of leakage power in 4×4 Wallace tree multiplier


INTRODUCTION
The multipliers play a major role in arithmetic operations in digital signal processing applications. The present development in processor design aim at low power multiplier architecture usage in their processor circuit. So the need for the low power multipliers has been increased. In past, device density and operating frequency were low enough, also that it was not a constraining factor in chips. When the scale of integration improves, more transistors, faster and than their predecessors are being packed into a chip. This leads to the steady growth of the operating frequency and processing capacity per chip, resulting in increased power dissipation, stated by Drakasan et al. (1992). There are three main sources for leakage current: • Source/drain junction leakage current • Gate dielectric tunneling leakage • Subthreshold leakage through the channel of an off transistor The junction leakage occurs from the source or drain to the substrate through the reverse-biased diodes when transistor is OFF. The magnitude of the diode's diffusion and leakage current density, which in turn, determined by the process technology.
The gate direct tunneling leakage flows from the gate through the "leaky" oxide insulation to the substrate. Its magnitude increases exponentially with the gate oxide thickness and supply voltage VDD.
The subthreshold current is the drain-source current of an OFF transistor. This is due to the diffusion current of the minority carriers inn the channel for MOS device operating in the weak inversion region.
In this study, we present a gate replacement technique that reduces the overall leakage power in 4×4 Wallace tree multiplier. The focus of this study is on leakage current reduction in standby mode of operation by replacing gates at worst leakage state.

MATERIALS AND METHODS
Here we briefly survey the different techniques used to reduce leakage power in 4×4 Wallace tree multiplier. Many techniques thus have been proposed recently to reduce the leakage power consumption.   Khandelwal et al. (2005) reported that dual threshold voltage process uses devices with higher threshold voltage along noncritical paths to reduce leakage current while maintaining the performance. Khandelwal and Srivastava (2004) stated that Multiple Threshold CMOS (MTCMOS) technique places a high Vth device in series with low Vth circuitry, creating a sleep transistor Assaderaghi et al. (1997) reported that, in the dynamic threshold MOS(DTMOS), the gate and body are tied together and the threshold voltage is altered dynamically to suit the operating state of the circuit. Another technique proposed by Kuroda et al. (1996) is to dynamically adjust the threshold voltage in the Variable Threshold CMOS (VTCMOS). Thus in all the above techniques there is a requirement of process technology support.
Another technique for leakage power control is power-gating approach proposed by Agarwal et al. (2006). This technique turns off the devices by cutting of their supply voltages. Moreover, bulky PMOS and/or Science Publications JCS NMOS devices (sleep transistors) are introduced in between either supply or ground and circuit. Introduction of sleep transistors creates virtual power and ground rails in the circuit. The sleep transistor is turned on while circuit is in active state and turned off when circuit is in idle mode. This is done with the help of sleep signals. Yuan and Qu (2006) reported that the he Input Vector Control (IVC) technique is applied to reduce leakage current at circuit level with little or no performance overhead. Recently Lee et al. (2003) observed that gate oxide leakage is also dependent on the input vectors to a CMOS gate. Besides, the maximum and minimum leakage vectors are same for both subthreshold leakage and gate leakage.
The 4×4 Wallace tree multiplier with full adder method replaces the full adders in the place of half adders. So there is no need for separate final summing system as shown in Fig. 1 and 2. Hence the total leakage power is reduced, which is stated by Radhakrishnan (2001).
In this study we present a gate replacement technique to reduce the leakage power in 4×4 Wallace tree multiplier Experiment results obtained from the proposed method described later in this study is compared with 4×4 Wallace tree multiplier with full adder.

Proposed Work
A 4×4 Wallace tree multiplier circuit is designed using 2-input NAND gate. The circuit is sufficiently large consisting of 12 full adders. When designed with only NAND gate it has 266 2-input NAND gate, totaling of 1064 transistor. In our method, We use cadence spectra to measure the overall leakage current in a CMOS gate that includes both subthreshold leakage and gate leakage. The below shown Table 1 and 2 lists the overall leakage current in 2-input NAND and 3-input NAND gate.

Gate Replacement Technique
The essence of gate replacement technique is to replace a logic gate which is at its Worst Leakage State (WLS) by another library gate.

Algorithm for Searching and Replacing Gates at WLS
Step 1: for each gate G,∑ {G1,G2…} Step 2: if (Gi is at WLS and not marked) Step3 : include Gi in the selection S; Step 4: while (there is new addition to S) Step 5: for each newly selected gate G in S Step 6: if (there exists library gate Ĝ meets the condition to reduce leakage) Step 7: temporarily replace G by Ĝ; Step 8: if (output of G is changed due to replacement Step 9: include G's unmarked fanout gate Gj in S; Step 10: compute total leakage change of gates in S; Step 11: if (there is leakage reduction) Step 12: mark all gates Gj in the section S; Step 13: make replacement in lines7, 9 or10 permanent; Step 14: else mark gate Gi only; Step 15: empty the section S Step 16: else mark Gi if it has not been marked yet: This algorithm is used to search the worst leakage gate in 4×4 Wallace tree multiplier. It find the 2-input NAND gates at worst leakage state and replaces them by 3-input library NAND gate. This technique introduce a sleep signal at the worst leakage gate. The complement of the sleep signal will be given as the third input to the 2-input NAND gate during standby mode of operation. So the output is not affected during active mode of operation because sleep signal signal value is logic one. By comparing Table 1 and 2 it shows that by given complement of sleep signal as the third input for the 2-input NAND gate the leakage current is drastically reduced during the standby mode of operation. By reducing leakage current in worst leakage state gates the overall leakage current in 4×4 Wallace tree multiplier is reduced.

RESULTS
The gate replacement technique was implemented and tested on 4×4 Wallace tree multiplier using full adders. Hence we use cadence spectra using 100 nm to measure the overall leakage current in 4×4 Wallace tree multiplier. This technique provides 43% of reduction in leakage current when compared to the base case.

DISCUSSION
Here gate replacement technique is compared with the 4×4 Wallace tree multiplier with full adder.
From Table 3 it is shown that 43% of leakage current is reduced by using gate replacement technique.

CONCLUSION
The leakage current of 4×4 Wallace tree multiplier was reduced by replacing half adders by full adders. But the leakage current was high during the standby mode of operation. In order to reduce this leakage current, we present gate replacement technique which reduces 43% of leakage current in 4×4 Wallace tree multiplier with full adders and the designers can add the sleep signal in non-critical pats there by not affecting the overall circuit delay, while significantly saving the overall leakage power.