OR-Bridging Fault Identification and Diagnosis for Exclusive-OR Sum of Products Reed-Muller Canonical Circuits

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INTRODUCTION
Any arbitrary logic function, in general, can be expressed in Reed-Muller Canonical (RMC) form as: F = (a 0 ⊕ a 1 x 1 * ⊕ a 2 x 2 * ⊕…⊕ a n x n * ⊕ a n+1 x 1 * x 2 * ⊕…⊕ a m x 1 * x 2 *…x n *) where, x n * can be x n or its complement, a n is either 0 or 1 and m = 2 n -1. However, there can be variations in such form. Of these, the Exclusive-OR Sum-of-Products (ESOP) form with the least number of product terms and hence needing least number of AND gates, is very much suitable for hardware implementation.
Single non feedback OR Bridging faults involving two lines at a time of the control and data inputs only are considered. Zhongliang (2002) demonstrated that single stuck-at fault detection can be achieved with only n +5 test vectors. In this study, it is shown that bridging fault detection and diagnosis can also be achieved with the same n+5 test vectors through MATLAB simulations for a few specific functions. Two quantitative indices, called identifiability factor and distiguishability factor are considered for comparison of the testability nature of given circuits. The identifiability factor is defined as the ratio of the number of faults correctly identified by the test set to the total number of possible faults of the type considered. The existence of faults can be recognized from the set of outputs measured which will be different from the fault-free circuit.
The distinguishability factor pertains to the identical set of outputs among different faults but the output set of each being very much different from the non-faulty case. The existence of even a large percentage of indistinguishability may not mean the circuit is not reliable, since it is still possible to identify the faulty condition of the circuit and take appropriate remedial action. The set of binary values for an output is converted into its decimal equivalent for convenience in comparison and ease of tabulation.
Literature survey: A classical method of generating test patterns for very large and complex logic functions is Linear Feedback Shift Register (LFSR) based pseudo-exhaustive or pseudo-random type Kalay et al. (2000). However, this does not work well with ESOP form as shown by Drechshler et al. (1997). A Positive Polarity Reed-Muller network for detection of stuck-at faults with a universal test of size n+4, n being the number of data inputs, was proposed by Reddy (1972). Though quite good for self-testing, the method is economical only for the specified form, which obviously has more number of product terms than the other forms in most cases. Multiple stuck-at fault detection for ESOP circuits was carried out by Pradhan (1978). However since the cardinality is 2n+6+ ∑nC e , e = 0 to j, the order of ESOP expression, the test set is not universal and also is too large to be practical for large input functions.
Stuck-at and bridging faults with a universal test set for Positive Polarity Reed-Muller network has also been reported Bhattacharya et al. (1985). Multiple fault detecting GRM realizations was propounded by Sasao (1997). It was shown that 2n+s+3 test vectors, where s is the number of product terms in the logic function are required for single stuck-at fault detections in Generalized Reed-Muller/ESOP circuits while 2n+s vectors are required for detection of and/or bridging faults in such circuits Zhongliang (2003). Here too, the test set is not universal as it depends on s, the number of product terms of the function. Kalay et al. (2000) described an ESOP implementation with a universal test set of size n+6 for single faults. A robust and universal sequence has been proposed for stuck-open type of faults in GRM/ESOP cmos implementations Rahaman et al., (2004). Zhongliang (2002) demonstrated that the single stuck-at fault detection can be achieved with only n+5 test vectors. Two methods, each with a small modification in this scheme in ESOP RMC circuits had been proposed by Neelakantan and Jeyakumar (2006a) for analysis and diagnosis of single stuck-at faults. This study is an extension of the work done by Neelakantan and Jeyakumar (2006b) for the analysis and diagnosis of OR-bridging faults in any of the pairs of data and control lines of the ESOP RMC circuits.

MATERIALS AND METHODS
Network structure: The network structure of the scheme is the same as that proposed by Zhongliang (2002) and Wu et al. (1996) is shown in Fig. 1. It comprises literal complementing XOR block, an AND block, an XOR function tree block, which implements the required logic function as also two additional outputs O 1 and O 2 obtained through a separate AND and an OR gate. The actual data inputs to the system are x 1 , x 2 …. x n . Additionally, the scheme requires four control inputs c 1 to c 4 . The literal-complementing block produces the complements of the literals used in the function. Only those literals appearing in complemented form require an XOR gate in this block.
The literals of each product term are combined through an AND gate and hence the number of AND gates required is the same as the number of product terms in the logic function. Further, each of the AND gates of this block has an additional input from one of the control lines depending on the number of gates used in the XOR tree block producing the final function F. Finally, all the data and control inputs are applied to a separate AND gate and an OR gate, producing auxiliary outputs O 1 and O 2 , to aid in the detection of faults which cannot be differentiated by the main function output F alone.
The required control lines are determined as follows using Fig. 2. Draw the XOR gate tree for the required product terms of the given function. Assign the numerals 1, 2 and 3 respectively to the two inputs and the output of the final XOR gate producing the function output F. Consider each XOR gate connected to the inputs of the final XOR gate considered. Assign the outputs of these XOR gates with the same numbers as the inputs of the final XOR gate. If the output of the XOR gate considered is 1, then assign 2 and 3 to its inputs. Else if the output is numbered 2, assign 3 and 1 to its inputs. Now consider the next earlier input stage and assign the numerals in the similar manner according to the output points connected.

Test vectors:
The test set has (n+5) vectors; each of the vectors is (n+4) long, 'n' being the number of data inputs. The first four columns of the matrix represent the control inputs c 1 to c 4 while the remaining n columns that of the data inputs are x 1 to x n . The generalized test set is shown in Fig. 3. The network and the set of test vectors for the specific function F = x 1 ⊕ x 2 x 3 ⊕ x 1 'x 2 x 3 are shown in Fig. 4 and 5 respectively.

Algorithm:
Step 1: Set up the circuit as in Fig. 4.
Step 2: Determine and connect the control lines c 1 to c 4 as explained.
Step 3: Apply the test vectors as given in Fig. 5, one by one.
Step 4: For each test vector, determine the three outputs F, O 1 and O 2 .
Step 5: Obtain the decimal equivalents of each of the above binary output sets.
Step 6: Simulate the specified type of fault at any pair of the control/data inputs.
Step 8: Compare the set of outputs with the predetermined fault-free condition outputs Step 9: If the two output sets match exactly, it implies that a fault, if present, is not identifiable or detectable; else, the fault is a detectable one.
Step 10: Repeat steps 5 to 8 for the specified type of fault at the other control and data inputs.

Numerical illustration:
Function considered: F = x 1 ⊕ x 2 x 3 ⊕ x 1 'x 2 x 3 Fault-free output set {F, O 1 , O 2 } = {126, 112, 127} The outputs of OR-bridging faults at lines c 1 in combination with c 2 , c 3 , c 4 , x 1 , x 2 and x 3 with post fault values 00 and 11 are tabulated in Table 2   Hence overall distinguishability factor is: However, when the individual cases are considered the distinguishability factor can be seen to be appreciably high as illustrated in Table 1.
Same output set of {86, 0, 127} for the following fault combinations: OR bridging fault with prefault value 0 at c 2 x 2 OR bridging fault with prefault value 0 at c 2 x 3 OR bridging fault with prefault value 0 at x 1 x 2 OR bridging fault with prefault value 0 at x 1 x 3 The distinguishability for this set is: Similarly, the output set {38, 0, 255} occurs 3 times, for which the distinguishability factor is (42-3)/42×100 = 92.86%.Though the overall distinguishability is small, it does not affect the detection capability. Further, the distinguishing capability for an individual output set can be quite high, as illustrated above.
Further, the location of fault can also be easily diagnosed from the output set. For instance if the output set is {86, 0, 127} then the fault condition would be one of the four cases discussed above involving c 2 , c 3 , x 1 and x 2 and hence those lines only need to be checked.

CONCLUSION
A test set scheme for detection of OR-bridging faults for ESOP RMC logic functions have been proposed and the simulation results show that the proposed scheme reduce the possibility of unidentifiable faults for the specified type of function. The location can also be diagnosed through the output set. The analysis and diagnosis have been done through compact tabulation and two quantification indices. All possible combinations of the data and control line pairs have been considered.