Braun’s Multipliers: Spartan-3AN based Design and Implementation

: Problem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The Sparatn-3An FPGA resources utilization for 4×4, 6×6, 8×8 and 12×12 bit Braun’s multipliers are obtained and Analysis Of Variance (ANOVA) presents that the 12×12 multiplier has significant difference than other three multipliers. The mean delay time for four multipliers shows that as the size of multiplier increases the mean delay time also increases. Conclusion: In essence, parallel multipliers based on the FPGA technology can provide better solution for DSP processor, medical imaging and multimedia.


INTRODUCTION
Real time imaging processes require intensive scientific computations for Digital Signal Processing (DSP). Fast and efficient parallel multipliers are required for DSP, General Purpose Signal Processing (GPSP) and application specific architecture for DSP. DSP algorithm implementation demands using Application Specific Integrated Circuits (ASICs); costs for ASICs are high as well as algorithms should be verified and optimized before realization. The contemporary Field Programmable Gate Arrays (FPGAs) have emerged as a platform for efficient hardware implementation of such complex and computation intensive algorithms.
There have been reported a number of studys on low power multiplier designs; such as investigation of different multiplier structures (Stouraitis and Paliouras, 2001) introduction of AND gates into multipliers to avoid unwanted spurious transition through the carry save array (Saravanan and Madheswaran, 2008) and switching activity and area of multipliers could be reduced through truncation of the lest significant bits (Rais, 2009a;Rais, 2009b;Rais, 2010a;Rais, 2010b;Rais et al., 2010c;Rais and Al Mijalli, 2011a;Rais and Al Mijalli, 2011b).

MATERIALS AND METHODS
Architecture platform: For hardware implementation of intensive computations require parallel nature, high frequency and high density of modern platforms. Thus FPGAs are the suitable platforms for such realization of computationally intensive and massively parallel multiplier architecture. Here brief introduction about Spartan-3 FPGA from Xilinx is presented.

Spartan-3 FPGAs:
Xilinx family includes Spartan-3 FPGA (Xilinx, 2009) as their fifth generation. Spartan-3 is purposely designed to meet the requirements of high volume, low unit cost electronic systems.
The family comprises of eight member offering densities ranging from 50,000 to five million system gates. The Spartan-3 family includes L, E, A and -3A DSP, Spartan-3AN and the extended Spartan-3A FPGAs.
Specifically, the Spartan-3AN is used as a target technology in this study. Spartan-3AN combines all the feature of Spartan-3A FPGA family plus leading technology in-system flash memory for configuration and nonvolatile data storage.
Braun's multiplier: Braun's multiplier is an n×m bit parallel multiplier and generally known as carry save multiplier and is constructed with m×(n-1) addres and m×n AND gates. The Braun's multiplier has a glitching problem which is due to the ripple carry adder in the last stage of the multiplier.
Basis of braun's multiplier: Consider a generic m by n multiplication of two unsigned n-bit numbers Y = Y m-1 …. Y 0 and X = X n-1 …X 0 The product P = P 2n-1 …P 1 P 0 , which results from multiplying the multiplicand Y by the multiplier X, can be written as follows:  Fig. 5 shows the mean delay time for the four multipliers, which clearly indicates as the size of multiplier increases the mean delay time also increases, the same result is obtained for truncated multipliers (Al Mijalli, 2011). Table 2 summarizes the FPGA device resources utilization for standard 4×4, 6×6, 8×8 and 12×12-bit Braun's multipliers. Table 3 shows the one-way ANOVA on Spartan-3AN FPGA device. The multipliers 4×4, 6×6, 8×8 and 12×12 are used for this analysis. The statistical analysis is done by using Statistical Package for Social Science (SPSS) program. There is a statistically significant difference at the .05 level in delay time for the multipliers (F (3, 16) = 76.034, p = 0.000). The mean values of delay time for the multipliers are compared by using one-way ANOVA and post-hoc Tukey HSD multiple comparison tests at the .05 significance level.       There is also significant difference between the delay time for multiplier 12×12 and the others three. However, the delay time for 4×4 multiplier does not differ significantly from 6×6 multiplier.

CONCLUSION
We have presented hardware design and implementation of FPGA based parallel architecture for standard Braun's multipliers utilizing VHDL. The design was implemented on Xilinx Spartan-3AN XC3S700AN FPGA device using the ISE 9.2i design tool. The objective of this study is to present the 4×4, 6×6, 8×8 and 12×12 bit Braun's multipliers and their resources utilization of Spartan-3AN FPGA. Furthermore, ANOVA is applied to see their latency effect in 4×4, 6×6, 8×8 and 12×12 bit Braun's multipliers. The ANOVA presents that the 12×12 and 8×8 multipliers have significant difference than other two multipliers. The delay time for 4×4 multiplier does not differ significantly from 6×6 multiplier. The mean delay time for four multipliers shows that as the size of multiplier increases the mean delay time also increases.