Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL

: This study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study’s main focus is on the speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a better performance over the multiplier with a ripple adder in terms of gate delays. Under the worst case, the multiplier with the fast adder shows approximately twice the speed of the multiplier with the ripple adder. The multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carry-look-ahead adder uses time = 659.292 ns.


INTRODUCTION
Multiplication can be considered one of the basic arithmetic operations. However, it is not as simple as addition or subtraction operations, because it takes more time to perform two subtasks, addition and shifting. Typically, a multiplication operation takes between 2 and 8 cycles [2] . Therefore, using high-speed multipliers is a critical requirement for processors with a high performance. The multiplier uses the addition operation for all the partial products. The adder can be a ripple adder, a carry-look-ahead adder, or any other adder [5,8] . However, using a fast adder for the multiplier improves the over all performance of the multiplication operation. Our study is focused on multipliers using unsigned data. VHDL, a Very High Speed Integrated Circuit Hardware Description Language, was used to model our multiplier design.
Several researchers had worked on the performance analysis of adders and other researchers on the performance analysis of multipliers. Sertbas and Selami worked on the performance analysis of classified binary adder architectures. They compared the ripple adder, carry-look-ahead adder, carry select adder and the conditional sum adder. They used VHDL in their comparison. Their study included the unit-gate models for area and delay [1] . Asadi and Navi developed a new 54×54 bit multiplier using a high-speed carrylook-ahead adder. Their proposed multiplier reduced the number of transistors, delay and power consumption [2] . Aziz and Kamruzzaman developed a synthesizable VHDL model for a generalized signed multiplier capable of performing multiplication of both signed-magnitude and two's compliment operands [3] .
Ripple carry adder: Ripple carry adders use multiple full adders with the carry ins and carry outs chained together, where the correct value of the carry bit ripples from one bit to the next [4] .
The two Boolean functions for the sum and carry are: We modeled this module with the following VHDL code: car(i+1) <= (a(i) AND b(i)) OR (car(i) AND (a(i) XOR b(i))) after gate_delay4; END LOOP; END PROCESS; cout <= car(32); END ARCHITECTURE; Carry look ahead adder: To reduce the delay caused by the effect of carry propagation through the ripple carry adder, we can attempt to evaluate quickly for each stage whether the carry-in from previous stage will have a value of 0 or 1 [4] .
Given the two Boolean functions for the sum and carry as follows: The propagate function Then C i+1 = G i + P i · C i The Carry Function Thus, for 4-bit adder, we can extend the carry, as shown below: C 1 = G 0 + P 0 · C 0 C 2 = G 1 + P 1 · C 1 = G 1 + P1 · G 0 + P 1 · P 0 · C 0 C 3 = G 2 + P 2 · G 1 + P 2 · P 1 · G 0 + P 2 · P 1 · P 0 · C 0 C 4 = G 3 + P 3 · G 2 + P 3 · P 2 · G 1 + P 3 · P 2 · P 1 · G 0 + P 3 · P 2 · P 1 · P 0 · C 0 In general, we can write: Unsigned multiplier: Multiplication involves the generation of partial products, one for each digit in the multiplier. These partial products are then summed up to produce the final product. The multiplication of two n-bit binary integers results in 2n-bit product. We can perform a fast multiplication by the number 2, by simply shifting the number one-bit position to the left. This is called a fast multiplication or bit shifting [5] .

VHDL simulation:
The VHDL simulation of the two multiplier are presented in this section. The VHDL code for both an unsigned multiplier using a fast carrylook-ahead adder and an unsigned multiplier using a ripple adder are generated. The VHDL model has been developed using the DirectVHDL simulator. The multipliers use 32-bit values. The worst case was applied using the two multipliers, where the gate delay is assumed to be 5 ns. The algorithms for the two multipliers are shown below:

Algorithm for a multiplier with a carry-look-ahead adder:
Begin Program Multiplier = 32 bits

CONCLUSION
Two different multipliers using a fast carry-lookahead adder and a ripple adder have been modeled and simulated using VHDL. The multiplier with a carrylook-ahead adder has shown a better performance over the multiplier with a ripple adder in terms of gate delays. In other words, the multiplier with the carrylook-ahead adder has approximately twice the speed of the multiplier with the ripple adder, under the worst case. In fact, the multiplier with the carry-look-ahead adder uses time = 659.292 ns, Fig. 1 [9] , while the multiplier with a ripple adder uses time = 979.056 ns, Fig. 2 [9] .