BDD path length minimization based on initial variable ordering

A large variety of problems in digital system design, combinational optimization and verification can be formulated in terms of operations performed on Boolean functions. The time complexity of Binary Decision Diagram (BDD) representing a Boolean function is directly related to the path length of that BDD. In this paper we present a method to generate a BDD with minimum path length. The Average Path Length (APL) and Longest Path Length (LPL) of the BDD are evaluated and discussed. The proposed method analyses the essentiality of a given variable order based on the complexity of sub functions derived from variable substitution. The variable that produces minimal cumulative complexity for the sub-functions is given priority over other variables. The experimental results and comparisons using benchmark circuits show that the proposed method is an encouraging approach towards minimizing the evaluation time of Boolean functions, consequently minimizing the time complexity of BDDs.


INTRODUCTION
For the last two decades, BDD have gained great popularity in representing discrete functions. BDD in general is a direct acyclic graph representation of Boolean functions proposed by Bryant and Akers [1,2] . The success of this technique has attracted many researchers in the area of synthesis and verification of digital VLSI circuits. Because of its efficiency in representing a variety of practical functions [3,4] , BDDs became very popular data structures. The efficiency of BDDs depends mainly on its size, which is the size of their graph representations. This size depends dramatically on the variable ordering adopted to build the BDD [5][6][7] . Finding an optimal variable order is often worth spending considerable computational efforts because this implies savings for further operations on the constructed BDD [8] . Some functions such as adders and depending on the variable ordering adopted, may lead to an exponential BDD sizes in terms of the number of input variables. Finding an optimal variable ordering is an NP-hard problem [9] . Another critical parameter during the construction of BDDs is the maximum memory requirement, which is directly proportional to the number of nodes. A good variable ordering can lead to a smaller BDD and faster runtime, whereas a bad ordering can lead to an exponential growth in the size of the BDD and hence can exceed the available memory [10] . Consequently, much attention has been devoted to techniques dedicated to finding good variable ordering. In general, variable ordering techniques fall into two categories: Static Variable Ordering (SVO) algorithms [11,12] and Dynamic Variable Ordering (DVO) algorithms [6,13] .
The evaluation time is also another important parameter, which uses BDDs to evaluate logic functions. The evaluation time is proportional to the path length in the BDD. Therefore, minimization of the path length can improve the performance of the circuit implementing a Boolean function, which will eventually enhance the performance of the final implementation. In general the minimization of the path length in Decision Diagrams (DD) is important in database structures, pattern recognition, logic simulation and software synthesis [14] . The methods proposed for the minimization of APL [14][15][16] reduces the average evaluation time of logic functions. Most of these methods are based on either heuristic variable ordering or dynamic variable ordering techniques. The minimization of APLs leads to circuits with smaller depth of paths from the Root to the Terminal nodes of the BDD. The resulting circuit will be optimized for speed on one hand and on the other hand the number of very long paths in the BDD will be reduced [17] . The minimization of APLs is of great importance in real time operating system applications [18][19][20] . The minimization of the LPL of a BDD can reduce the longest evaluation time, which is very important for Pass Transistor Logic (PTL) [21][22][23] . One of the main problems with pass transistor networks is the presence of long paths: the delay of a chain of n pass transistors is proportional to n 2 . Inserting buffers can reduce the path length, but this increases the silicon area. So the minimization of the longest evaluation time will improve the performance of the circuit [21,23] . In this study we propose an algorithm that minimizes the path length of BDDs. The resulting initial variable ordering will produce BDDs with the minimum possible APL and LPL, consequently reducing the number of nodes to an acceptable size. Hereafter, we introduce next the necessary terminologies and definitions, followed by the proposed method that computes the minimum APL and LPL of the BDD based on static variable ordering, experimental results and the conclusion of our study with an outline of our future work.

PRELIMINARIES
Basic definitions for BDDs are given in [1,2,24,25] . In the following we review some of these definitions.

Definition 1:
A BDD is a directed acyclic graph (DAG). The graph has two sink nodes labeled 0 and 1 representing the Boolean functions 0 and 1. Each nonsink node is labeled with a Boolean variable v and has two out-edges labeled 1 (or then) and 0 (or else). Each non-sink node represents the Boolean function corresponding to its edge "1" if v = 1, or the Boolean function corresponding to its edge "0" if v = 0.

Definition 2:
An Ordered BDD (OBDD) is a BDD in which each variable is encountered no more than once in any path and always in the same order along each path.

Definition 3:
A Reduced OBDD (ROBDD) is an OBDD with only two reduction rules: deletion rule and merging rule. The Reduction rules remove redundancies within the OBDD.
Variable Ordering: The size of a BDD is largely affected and its variation can be linear or exponential depending on the choice of the variable ordering in building the BDD. Figure 1 illustrates the effect of the variable ordering [1] on the size of BDDs for the Boolean function (1): Definition 4: In a BDD, a sequence of edge and nodes leading from the root node to a terminal node is called Path. The number of non-terminal nodes on the path is called the Path Length.

Definition 5:
The APL is equal to the sum of the node traversing probabilities of the non-terminal nodes [14,18] . Node traversing probability denoted by ) is the fraction of all 2 n assignments of values to the variables whose path includes node i v . The APL can be expressed by the following equation (2): Where, N is the number of non-terminal nodes. i e ) denotes edge "0" (or the edge "1") directed from away node i V [14] . Since all paths include the root node, this node is traversed with probability 1.00. Since all assignments to values of variables are equally likely, we can use the following equation to calculate the ) ( i V P for the rest of the nodes: Example: Consider the BDD graph shown in Fig. 2. In this example we will compute the APL and the LPL:

Definition 8:
In the DD of a logic function f , the memory size of the DD, denoted by Mem (DD), is the number of words needed to represent the DD in memory [18] . In a memory, each non-terminal node requires an index and pointers to the succeeding nodes. Since each nonterminal node in a BDD has two pointers, the memory size needed to represent a BDD is given by:

PROPOSED METHOD
The proposed method is a static variable ordering technique [26,27] , which uses the input Boolean expression to find the variable ordering used to minimize the APL and LPL. This is based on a single level Boolean function; hence, if a Boolean function is multilevel, then it is converted to a single level function prior to applying the proposed method. MVSIS (Multi Valued Logic Synthesis Tool) Version 1.0 is used for the conversion of Boolean functions from multilevel to single level. The proposed method consists of selecting the variable based on the complexity of sub-functions derived by assigning logic 1 and logic 0 to that variable. The variable that produces sub-functions with minimum complexity is given priority over other variables. The complexity of the sub-functions is evaluated based on the number of variables (NV), number of product terms (NPT) and the number of variable occurrences (NVO). Using this method we can produce the BDD graph with the shortest possible paths among all nodes including the terminal nodes, which will eventually reduce the path length. The complete steps of the proposed method are explained in the following algorithm: Step 1: Note the number of inputs (N) of the Boolean function with input variables Step 2: Set the variable counter (M) to 1 Step 3: Substitute logic 0 for variable X M in the input function Step 4: Simplify the resulting function using McCluskey's simplification method For each of the iterations described above, we note that the number of expressions increases but the complexity of the expressions decreases. This decrease in complexity reduces the procedure to find the variables that come next in the variable order. The obtained variable order is used to build the BDD and compute the APL and LPL using Colorado University Decision Diagram (CUDD) package [28] . The following example illustrates the proposed algorithm.
From Table 1, variable X 3 is selected as first variable in the order since it has the least total of NV compared to other variables. Two new sub-expressions (9) and (10) (9) and (10) we re-start the procedure to find the second variable of the order. Substituting logic 0 and logic 1 for the three variables x in expressions (9) and (10) we obtain the following sub-functions: Table 2 indicates the values of NV, NPT and NVO for the twelve sub functions. From Table 2 the variable x 1 is selected as next variable since it has the least number of total NV. It should be noted here that, so far in this example there was no need to check the parameters NPT and NVO, since NV was always the least. The first two variables are selected, hence, four sub-expressions are obtained from the substitution set (x 3 , x 1 ) = (0,0), (0,1), (1,0) and (1,1). The 4 subfunctions can be used to find the third variable of the order. Performing the same procedure described above one can find all the variables in the order. In our example, after going through all required steps we obtain the variables order . This variable order is used to build the BDD and find the APL and LPL.

RESULTS
Here we present two sets of results using the Colorado University Decision Diagram (CUDD) package [28] , on a Pentium 4 machine with 512 MB RAMs. The first set represents the results derived from three of the best CUDD variable ordering techniques (Symmetric Sifting, Swapping and Window Permutation) and the proposed method. The second set of results is a comparison between the proposed method and two available APL methods. All experiments were performed using selected ISCAS benchmark circuits [29,30] . In Table 3, 5 and 6, a comparison with CUDD methods was performed for the parameters APL, Mem (BDD) and LPL respectively. Table 4 illustrates the results of the comparison with the latest available methods for the minimization of APL. In each of the Table 3-6 the first column shows a list of selected ISCAS benchmark circuits we have used to demonstrate the performance of the proposed method. Table 3, columns 2, 4 and 6 illustrate the results obtained for three CUDD variable reordering methods, namely the swapping, symmetric sifting and window permutation in terms of number of nodes. Columns 3, 5 and 7 show the results in terms of APL. The results shown in columns 8 and 9 are from the implementation of our proposed method in terms of number of nodes and APL respectively. The minimum number of Nodes, the minimum APL and the number of nodes for the minimum APL are illustrated in columns 10, 11 and 12 respectively. The gain factors of each method against the minimum APL are given in columns 13, 14, 15 and 16.

Average path length: In
The results obtained indicate the efficiency of the proposed method compared to other CUDD methods in term of APL and number of nodes. In general, the results obtained in column 16 indicate the effectiveness of the proposed method, where a minimum APL gain is obtained for 97% of the circuits, compared to 26, 18 and 24% achieved by the Random Swapping method, the Symmetric Sift method and the Window Permutation method respectively.
Even though all the circuits equally benefit from the proposed algorithm, in some cases like i6, i7, X4, X2, alu2, pm1, 5xp1, sao2, mux, cm150a, cm162a, cm163a and cm151a, the reduction is such as to make a dramatic difference in the processing of the circuits.
The results indicate the potential of the proposed method, where it managed to minimize both the APL and the number of nodes for 52% of ISCAS benchmarks, i.e. i1, X2, apex4, b9, cm42a, decod, misex1, misex2, pm1, 9sym, z4ml, clip, majority, cm138a, mux, cm150a and cm163a.     Table 4 illustrates the benchmark results comparison with the previous work done in [14,16] . It can be inferred that the proposed method improves the APL in 100% of the benchmarks compared to [16], which uses three different algorithms, mainly bottom-up, topdown and middle-way, with the initial heuristic variable ordering. The proposed method was able to achieve improvement in the APL for 70% of the benchmarks compared to [14] , which uses dynamic variable ordering technique. Benchmarks 5xp1, f51m, Z4ml, cm85a, cm162a, cm163a, mux and cm150a proved to be gaining the maximum from the proposed method. In general the proposed method provides far better results than the method in [16] and gives more competitive results than the method based on dynamic ordering in [14] .

Memory size of BDD:
For each BDD the memory size is computed using the equation (4) and tabulated in Table 5. In this Table columns 2, 3 and 4 illustrate the memory size obtained for the same three CUDD reordering methods that were used before. The memory size needed for the BDD construction using the proposed method and the minimum memory size resulting from the use of all four methods are given in columns 5 and 6. The gain factors of each method against the minimum memory size are given in columns 7, 8, 9 and 10. It can be inferred that the proposed method managed to achieve the minimum memory size for 58% of the circuits against other reordering methods, which were mainly designed for the optimization of BDD size. Table 6, columns 2, 4 and 6 illustrate the results obtained for three CUDD variable reordering methods, namely the swapping, symmetric sifting and window permutation in terms of number of nodes and columns 3, 5 and 7 show the results for the same in terms of LPL. The results shown in columns 8 and 9 are from the implementation of our proposed method in terms of the number of nodes and the LPL respectively. The minimum LPL size out of all the methods is given in column 10 and the gain factors of the proposed method against the three CUDD methods are given in columns 10 to 12.

Longest path length: In
The obtained results indicate the efficiency of the proposed method compared to other CUDD methods in terms of minimum LPL. In general, the obtained results indicate that the proposed method managed to minimize the LPL for more than 90% of the benchmarks compared to the efficiency of 37, 27 and 63% of Swapping, Window Permutation and Symmetric Sift reordering methods respectively. On the other hand, when the limitations of BDD nodes are set, the proposed method can achieve a maximum reduction in both the number of nodes and the LPL of 53% of the BDDs compared to 10, 13 and 56% for Swapping, Window Permutation and Symmetric Sift respectively. Benchmark circuits i1, i6, i7, X2, Apex4, B9, Z4ml, clip, B12, mux and cm150a lead to a maximum gain with the proposed algorithm compared to all three CUDD methods. Benchmark circuits X4, cc, squar5, misex2 and cm151a achieve better gain than two of the CUDD methods and circuits alu2, decod, 5xp1, sao2, cm85a, cm162a and cm163a lead to equally good results compared to CUDD methods.
In general, the proposed method gives a higher probability of achieving the minimum path length for most of the medium scale IASTED benchmark circuits. The minimization of the APL and the LPL leads to circuits with a smaller depth in the paths from Root to Terminal nodes. On the one hand this will lead to optimize the circuit for speed and on the other hand reduce the number of very long paths. Since the path length is directly related to the evaluation time of logic design, the above results prove that the proposed method minimizes the evaluation time and the space complexity of the circuit, which will eventually minimize the cost of the design.

CONCLUSION
A new algorithm for minimizing the evaluation time in BDD has been developed. The algorithm has been implemented using ISCAS benchmark circuits and the results have been compared with the three CUDD reordering methods and two of the available methods for path length minimization. Experimental results indicate that this algorithm is promising, yielding better results than more mature reordering techniques for most of the benchmark circuits. Even though most of the minimization methods use dynamic variable ordering technique, the above results proved that the static ordering techniques, too, could lead to some competitive results for path length minimization. It is also quite clear that the minimization of the evaluation time of BDDs can improve the performance of the circuit and have a strong influence on the quality of the final implementation. Our future work and developments will concentrate on investigating the APL and LPL minimizations for larger scale benchmark circuits.