DFM of Strained-Engineered MOSFETs Using Technology CAD

: Problem statement: In this study, a systematic study based on Technology CAD (TCAD) was taken up for the design and Virtual Wafer Fabrication (VWF) of strain-engineered MOSFETs in Si CMOS technology. Approach: A simple manufacturable process recipe was developed to induce uniaxial stress in channel region to obtain enhanced performance in CMOS in 45 nm technology node. Results: Using Synopsys Sentaurus Process simulation tool, high dopant activation and low Transient Enhanced Diffusion (TED) during processing are fully captured. A physics-based mobility model had been developed and implemented in Synopsys Sentaurus Device tool. Sentaurus Device was used to simulate device DC and AC characteristics and also to extract V th , I on and I off . Conclusion: Optimum process conditions required to meet a set of device specifications had been achieved via the Design of Experiment (DoE) study. Process Compact Model (PCM) was used for performance and manufacturability optimization.


INTRODUCTION
As MOSFET device dimensions approach their physical limits (Maiti et al., 2007a), TCAD tools that can accurately simulate IC fabrication process technology and device characteristics are indispensable for advanced technology development and manufacturing. TCAD is now an integral part of Integrated Circuit (IC) manufacturing due to its predictive capability for the process, device and circuit simulations. TCAD has also the power to analyze accurately the impact of process parameter variations on device characteristics and may be used to address and control process variability as needed for modeling the semiconductor manufacturing process. During process modeling, generally a systematic Design of Experiments (DoE) run is performed. DoE can be systematically set up, with control over process parameters and arbitrary choice of device performance characteristics. The models developed from DoE are known as Process Compact Models (PCMs). They are analogous to compact models for semiconductor devices and circuits. PCM may be used to capture the nonlinear behavior and multi-parameter interactions in manufacturing processes.
In this study, we report on a systematic TCADbased study towards design and optimization of strain-engineered MOSFETs in 45 nm technology node using Sentaurus TCAD tools (Synopsys, 2008a;2008b). Sentaurus Process simulator have been used to perform process simulation. The development of the processstrain induced mobility model and its implementation in Sentaurus Device simulator have been described. The simulated DC and RF characteristics for Processinduced Strained-Si (PSS) p-and n-MOSFETs and a comparison with the reported experimental results are presented. We have also presented the results of the PCM studies via the variation of technological parameters for the optimization of strain-engineered MOSFETs.
In previous study (Abdallah and Nabhan, 2009), a switched-capacitor filter with a high stop band attenuation and low passband ripple is proposed and analyzed. Graphic-based simulation model of the DSSC is presented in PSCAD/EMTDC and using this model a harmonic analysis is carried out to define (Fajri et al., 2008).
The earlier study will reduce procedure of CT scanning and design time for patients with not very large or complex defect (Sena and Piyasin, 2008). Design of standardized skull implants therefore will help the surgeon in implant preparation, by selecting implant that matches well with each case.

MATERIALS AND METHODS
Sentaurus Process tool is used to simulate and optimize a typical 45 nm process flow, including channel, halo, Source/Drain (S/D) engineering, oxidation, deposition, etching and annealing for dopant activation. The stress history is calculated for the entire process flow. Strain sources are lattice mismatch (SiGe pocket) for PSS p-MOSFETs and intrinsic stress (compressive cap) for PSS n-MOSFETs. Source/drain SiGe pocket is formed with 17% Ge at room temperature and nitride cap layers are introduced after the critical doping steps and, therefore, have negligible impact on the final doping distributions. A three-stream diffusion model is used. Additionally, formation of pointdefect clusters and the three phase segregation model account for the dose loss at the silicon-oxide interface are considered. For simulation of ion implantation, a 2D analytic integration with dual Pearson (in silicon) and Pearson primary distribution functions (in other materials) is used. For the simulation of Ge diffusion and redistribution in strained-Si a model is used which supports structures with various regions containing strained-Si. At each diffusion step, the stress evolution is computed including oxidation steps based on the viscoelastic model. The strain calculation also includes the compression due to Ge incorporation. The Si 0.83 Ge 0.17 pockets induce uniaxial compressive stress in different areas of the structure, including the channel. This may be seen in the stress distribution after S/D anneal as presented in Fig. 1a. The nitride film transfers the stress to the channel because an edge force is developed as the film grows over the spacer and the gate. Figure 1b shows the device structure simulated with highly tensile cap layer and tensile stress in the channel area. The structure generated by Sentaurus Process is then simulated using Sentaurus Device. The simulated device performance includes: DC electrostatic behavior with strain-induced mobility enhancement and the impact of Rapid Thermal Annealing (RTA) on device performance. Table 1 shows the major process parameters used in simulation. Hydrodynamic transport model was used in device simulations.
Strain-induced mozbility model: In developing the strain-induced mobility model, we implemented strain effects by considering scattering of mobile charges in process-induced strained-Si n-and p-MOSFETs due to electron/hole-phonon interactions in strained-Si channel. To obtain the strained induced mobility, first we calculated strain-induced interaction potential scattering by acoustic phonon. Then we use Fermi's golden rule to obtain the electron/hole-phonon scattering rates. Towards this, one needs to obtain the matrix element for electron-phonon scattering. The matrix element describes the coupling between initial and final electronic states due to interactions with scattering charge centers. Finally, we integrate the matrix elements over all final states to obtain the scattering rate between electron/hole-phonon.
Strain-induced interaction potential scattering by acoustic phonon: In a deformed Si substrate the coordinates of its lattice point are displaced. If the radius vector of a lattice point in undeformed condition is r and in deformed condition is r / , then the displacement vector is given by:  The deformation may be described in terms of symmetrical strain tensor as: If the distance between two lattice points of an undeformed Si substrate is dl, of the deformed Si substrate (strained-Si substrate) is dl / , then we get: and: ( ) ( ) The tensor du i determines the variation of distances between the lattice points. Neglecting the quantity 2 i du and expressing du i in terms dx m : and combining Eq. 3-5 we obtain /2 dl as: Taking into account Eq. 2 we obtain for /2 dl : We may write from Eq. 7: The variation of volume upon deformation is given by: V dx dy dz dx 1 u dy 1 u dz 1 u V 1 u u u Therefore the local dilation ∆r is given by: Above local dilation is equivalent to displacement of the atoms and hence equivalent to a local change of lattice parameter. Therefore, it induces a modification of both the bands: (a) valance band (E C ) and (b) valance band (E V ). The interaction potential AC e ph H − of the acoustic phonon with the lattice depends on the variation of conduction band and valance band edge. Since phonons deform the crystal in three dimensions, we can assume for small stress and for an isotropic crystal, interaction potential is given by: where, Ξ is the so-called deformation potential. The lattice displacement u(r) for long wavelength phonon is given by (Kittel, 1987): Where: ρ = The semiconductor density q w = The polarization vector For longitudinal phonons, the polarization vector is q qŵ q q = = . Thus the acoustic deformation potential may be written as: Transition probability for acoustic phonon scattering: The scattering rate of electrons or holes by lattice vibration in presence of strain may be explained in terms of the corpuscular model with the aid of phonon concept. Charge carriers colliding with phonons exchange energy and quasi-momentum with it. Since the number of phonon depends on temperature, the charge scattering should be temperature dependent. However, in order to calculate the quantum transitions of electrons and holes from state to state, the perturbation generated by deformation potential due to strain should be applied. Once we have the acoustic deformation potential, one may obtain the scattering rate using Fermi's golden rule: where, f and i refer to final and initial states. The energy of lattice vibrations under electrons or holes phonon interaction may change by the creation or annihilation of phonon. Hence, in collisions the initial and the final energies of the electron/hole-phonon system are: Hence, transition probability for the state E k to E k / in an electron/hole phonon collision involves phonon in the wave vector q is: Strain-induced scattering matrix: If k (r) ψ is the eigenfunction for the unstrained condition and k (r, ) ψ ε is the eigenfunction for strained condition, then: Now the scattering matrix elements for long wavelength acoustic phonon scattering in isotropic material are given as (Roblin and Rohdin, 2001): Now, considering: ( ) q q 1 q q 1 † q n q n q n q n a n , a n 1 Where: † q a and α q = The creation and annihilation operator ψ k and φ q = The wave function of the electron and lattice vibration mode of vector q Now substituting Eq. 19 and 20 in 18, one obtains: i(k q k ).r * * * * k n 1 q k n 1 k n k n i(k q k ).r q (k , k) i (w .q) 2 u u (r) n e u u (r) dV n 1e Relaxation time for acoustic phonon scattering: The well known equation to define relaxation time is given by (Nag, 2001): Replacing and combining Eq. 16, 18 and 22 we get the following expression as: where, n q represents the occupation number of acoustic phonons with wave vector q . Since an electron or hole may change its state from k by emission or absorption of an acoustic phonon of energy q ω ℏ , there are two terms involved in Γ / k → k corresponding to these two types of transitions. Since / k k q = + , the integral may be also carried out in q-space. τ may therefore, be written as: The element of volume dq in q-space may be expressed in spherical coordinate system as: For the sake of convenience the direction of k is taken as the polar axis and the azimuthal angle φ is measured with reference to plane containing the direction of the field and the vector k as shown in Fig. 2. Thus we get: For the uniaxial strain-induced transformation of the isoenergetic surface, the deformed spheres transform into the oblate ellipsoid in the heavy-hole band and elongated ellipsoid in the light holes band (Kolomoets et al., 2009). For this case Ξ is function of β, i.e., ( ) Ξ β and: For the azimuthal average approximation we can take ω q = νq where ν, is velocity of the mode averaged over direction. Regarding n q , a simple case is considered and most commonly applicable is the case of equipartion and is given by: Since there is energy and momentum conservation limit, we take q min = 0 to q max = 2k, a typical phonon energy is vk ℏ . When q n 1 ≫ , the rates for absorption and emission become almost identical. Substituting Eq. 27 and 28 in 26 and using above approximations for a spherical band, one obtains: However, semiconductors having ellipsoidal constant energy surfaces (for uniaxial strain), the matrix element for the acoustic phonon scattering is not isotropic. It is found that the relaxation time for this case may be expressed in two components, one perpendicular to the axis of symmetry of band structure and the other parallel to it. Using the relation ρν 2 = S ij , where S ij is the elasticity constant modulus, the components may be expressed as:  [j] in the parameter file in the device simulator. The values of S 11 , S 12 and S 44 are 1.23×10 12 , -4.76×10 12 and 0.8×10 12 respectively (Synopsys, 2008b). Total deformation potential constant ( ) Ξ for conduction and valance bands were taken as 9.5 and 6.6 eV, respectively (Sun et al., 2007). For the case with 500 MPa uniaxially compressive stress in Si, E k was assumed to be 25 meV. Scattering by neutral centre, scattering by impurity ion were also considered in simulation. As all the mechanisms are independent of each other, the total scattering probability is equal to the sum of probabilities of scattering by scattering centers of all types. Hence, the mobility model is given by: The above mobility was considered in hydrodynamic model and was implemented in the Sentaurus Device simulator. To activate the mobility model, appropriate mobility values were defined in the fields of the parameter file of the device simulator. The simulated hole mobility Vs. electric field for processinduced strained-Si p-MOSFET is shown in Fig. 3. Our simulation data for the drain current (I ds ) Vs gate voltage (V gs ) have also been calibrated against reported experimental data (Ghani et al., 2003).

RESULTS AND DISCUSSION
In this stury, the impact of a strained-Si channel on device performance is evaluated in Sentaurus Device in which the mobility model has been incorporated. with reported experimental device data (Ghani et al., 2003) Fig. 5: Comparison of simulated and experimental (Ghani et al., 2003) integrated film stress and resultant I Dsat improvement as a function of film thickness The MOSFET structures with embedded-SiGe (e-SiGe) Source/Drain layers for p-MOSFETs and a highly tensile silicon-nitride cap layer for n-MOSFETs used in simulation were chosen from the reference (Ghani et al., 2003) as reliable experimental data are available for benchmarking and validating the predictive simulation results. Briefly, the MOSFETs have a gate length of 45 nm with 1.2 nm gate oxide. Experimental data were reported for two different drain biases and the measured drain current vs. gate voltage is shown Fig. 4 along with our simulation results. A good agreement is observed showing the prediction capability of TCAD simulation. Figure 5 shows a comparison between simulated and measured integrated film stress and the resultant process-induced strained-Si n-MOSFETs drain current (I dsat ) improvement as a function of film thickness. Figure 6 shows the I d -V ds characteristics of the 45 nm MOSFETs with and without strained-Si channel. For the n-MOSFETs, the simulated results indicate an approximately 23% increase in drain current at V ds = V gs = 1.2 V due to an enhancement in electron mobility as a result of the strain in the channel. An empirical relationship between the strain components and the linear drain current has been reported in reference (Maiti et al., 2007b). The change in linear drain current for p-MOSFETs may be expressed as (Yeo et al., 2004): dlin x xx y yy z zz dlin I a a a I where, a x , a y and a z are the strain sensitivity coefficients with respect to the x, y and z strain components, respectively. Since ∆I dlin /I dlin ≈∆µ/µ, the mobility enhancement is approximately the same as the linear drain current enhancement. Using the Eq. 32, we have computed the electron and hole mobility enhancement factor due to tensile and compressive longitudinal stress for strain-engineered n-or p-MOSFETs, respectively. For the PSS p-and n-MOSFETs hole and electron mobility enhancement factor have been found to be ~1.5x and ~1.8x than that of bulk-Si, which is also consistent with our simulation results. The resulting simulation demonstrates an approximately 17% enhancement in drain current with respect to the bulk-Si p-MOSFETs. An AC simulation is performed at equidistant bias points from small-signal AC analysis at various frequencies, with the gate as the input port, the drain as the output port and the source and substrate grounded. The resulting small-signal admittance and capacitance parameters are then used to extract RF Fig. 7 of merit, such as the cut-off frequency (f T ). The bias dependence of f T is shown in Fig. 7.
Process optimization for strain-engineered MOSFETs using process compact model: Process variability has become a primary concern with regard to manufacturability and yield. As device dimensions shrink, the sensitivity of device performance to process variation also increases. With 45 nm processes, it is imperative to develop a systematic TCAD-based methodology to design, characterize and optimize manufacturability to increase yield (Montgomery, 2000). As the manufacturability of a process technology may be evaluated by the process window, defined as the area between the lower and upper limits of the critical process variables that yields acceptable device performance, in the following, we use the Sentaurus Process Compact Model (PCM) studio for the strainengineered MOSFETs.
For the determination of the influence of tolerances in the technology process optimization different process parameters have been varied. Before running the systematic TCAD simulations, a sensitivity analysis is performed to determine the critical process variables and suitable ranges for the experimental design. Figure 8a and b illustrate the sensitivity of the p-and n-MOSFET responses with respect to the halo implant dose, respectively. Figure 9 shows a normalized histogram plot summarizing the sensitivity analysis for the critical process steps.
To demonstrate process optimization using PCM studio, one device parameter, e.g., threshold voltage (V t ) is chosen and the process is optimized with respect to V t . As an example, we optimize the device performance by minimizing threshold Voltage (V t ) which mainly depends on the following parameters; Halo implant Dose (Halo_Dose) and Extension implant Dose (Ext_Dose), gate length (L g ); gate oxide thickness(Gox), peak temperature for Rapid Thermal Annealing (RTA) which modifies the doping concentration in the channel region. The optimization problem consists of finding the best combination of the above parameters that produces the desired threshold voltage. The visual optimization procedure allows one to put constraints on the input parameters which however, are motivated by the manufacturing considerations. For an example, we may set a minimum for the gate length to obtain a nominal threshold voltage. The combination of Sentaurus Process, Sentaurus Device, PCM studio and Sentaurus Workbench, forms a powerful Design for Manufacturing (DFM) TCAD environment. In this study, a total of 1200 experiments were generated. The process and device simulation results are subsequently used as the basis for generating a Process Compact Model (PCM), which encapsulates the relationships between input (design) and output parameters. The PCM automatically correlates design parameters to the tolerances. The ranges are normalized to 1 (Fig. 9), with the center representing the nominal value for each parameter. Table 2 summarizes the parameters and ranges chosen to optimize strainengineered MOSFETs, including the names used as references in.
The process was optimized with respect to threshold voltage, channel stress, device current and transconductance. Parallel coordinate plots link the simulation results to the design variation. The parameter values and ranges indicate whether the domain has been covered sufficiently. The yellow region is the constraint of the parameters and the outputs that satisfy the range of design specifications. Red lines within this region depict the successful design.
For the case study of p-MOSFET threshold voltage optimization, we allowed a threshold voltage variation within 0.007-0.243 V. We put a variation limit on gate length by narrowing the experiment selection resulting in a 5% lower V t compared to the nominal value. We select only lower V t which means reducing on-state voltage. The optimization procedure is continued and finally we perform a further screening on germanium mole fraction for process-induced strain-engineered p-MOSFETs and nitride cap layer for process-induced strain-engineered n-MOSFET, resulting in a combination that gives Ge mole fraction and SiN thickness, generating the optimized V t . By repeating the above optimization procedure, the device performance may further be improved to obtain V t within 1%. The process conditions satisfying the specifications for V t indicated in red in the parallel coordinate plot provides information about how well the domain space is covered with the chosen DoE.  Fig. 10: Parallel coordinate plot. The process is optimized with respect to threshold voltage, current and transconductance for processinduced strained-Si (a) p-and (b) n-MOSFETs Figure 10a and b show the Process Compact Model (PCM) evaluation scenarios for process-induced strainengineered p-and n-MOSFETs, respectively. Figure  10a is a parallel coordinate plot that links the simulation results to the design variation of the gate Length (L g ) and Germanium mole fraction (Ge) in embedded-SiGe source/drain region for process-induced strainengineered p-MOSFETs. Similarly, Fig. 10b is a parallel coordinate plot that links the simulation results to the design variation of the gate length (L g ) and cap layer thickness (SiN) for process-induced strainengineered n-MOSFETs. However, more advanced analyses are possible, including fluctuation analysis of different fabrication processes, leading towards the optimization of manufacturing yield. The above DFM/PCM simulation example demonstrates how to optimize a process and to reduce the process development time by reducing the number of costly and time consuming design iterations.

CONCLUSION
With extreme scaling down of MOSFETs in high volume manufacturing, it is imperative to develop a systematic TCAD-based methodology to design, characterize and optimize manufacturability to increase yield. Sentaurus Process and Device simulators are used to simulate DC and AC characteristics and Sentaurus Workbench Visualization is used to extract device parameters such as V th , I on , I off and RF parameters. Process Compact Model has been used to find the optimum process conditions to meet a set of device specifications for strain-engineered MOSFETs. The interactive visual optimization process using design of experiments in a parallel coordinate plot allows one to explore device performance criteria. Utilization of TCAD tools for process optimization for overall Design For Manufacturing (DFM) solution is demonstrated.

ACKNOWLEDGEMENT
The study has been supported by MCIT/DIT, N. Delhi.