A Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection Ratio

Problem statement: High speed operational amplifier is always an on-go in research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0 .5 μm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure st ability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain , a 24 V μS slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMO S operational amplifier in Jordan as the authors are aware, is we ll-suited to low-voltage applications since it does not require cascade output stages.


INTRODUCTION
The two-stage circuit architecture has historically been the most popular approach for both bipolar and CMOS op amps, where a complementary process that has reasonable n-type and p-type devices is available (Roberge, 1975). Although this study includes a CMOS version of a two-stage op amp, a bipolar version is similar but slightly more complicated. The two-stage op amp is characterized by its excellent performance when resistive loads need to be driven (Steininger, 1990).
In this study, a two-stage op amp with a high CMRR and a high unity gain frequency is proposed and analyzed. The proposed op amp includes three cascaded stages-two gain stages and a unity-gain output stage necessary for driving resistive loads. The proposed circuit has an open-loop gain of 84 dB, a CMRR of 84 dB, a slew rate of 24 V µS −1 , a unity-gain frequency of 30 MHz and consumes 2.8 mW.

MATERIALS AND METHODS
Architecture and circuit implementation: Figure 1 shows the block diagram of the proposed CMOS op amp. It consists of three cascaded stages-two gain stages and a unity-gain output stage necessary for driving resistive loads. The first gain stage is a differential-input singleended output stage. The second gain stage is a common-source stage that has an active load. Capacitance C is included to ensure stability when the CMOS op amp is used with feedback. The third stage is a unity-gain stage utilized for driving resistive loads. The complete circuit diagram of this op amp is illustrated in Fig. 2. A brief description of the utilized circuits follows. Am. J. Engg. & Applied Sci., 3 (1): 189-192, 2010 Differential-input first stage: The differentially input single ended output stage is formed by the p-channel MOS transistors M1 and M2, loaded in a current mirror formed by the n-channel MOS transistors M3 and M4. Utilizing the p-channel MOS input transistors for this stage is always the best choice to maximize the slew rate since p-channel MOS transistors have low mobility factors. We consider the slew rate an important feature of op amp design. Our choice of p-channel transistors in the first stage will also minimize the flicker noise. The gain of this stage can be expressed as: Common-source second stage: The second stage is simply a common-source gain stage with a p-channel active load M6. This stage has an n-channel input drive transistor M7. This arrangement maximizes the transconductance of the drive transistor in this stage and therefore increasing the unity-gain frequency of the op amp. Such parameters are critical when high frequency operation is desired. The gain of this stage is given by: Output buffer third stage: The stage is a commondrain buffer stage. In this source follower, the source voltage follows the gate voltage of M8. As shown, the body substrate of M8 is at the same voltage as the source of M8 to eliminate the gain degradations due to the body effect. This connection also results in a smaller dc voltage drop from the gate to the source of M8, which is considered as a major limitation on the maximum positive output voltage. The gain of the source-follower stage is given by: Biasing circuitry: It is well known that transistor transconductance is an important parameter in op amps that must be stabilized. This stabilization can be achieved by the bias circuitry shown in Fig. 2. In this circuit, the transistor transconductances are matched to the conductance of a resistor. As a result, the transistor conductances are independent of power supply voltage as well as the process and temperature variations.
For the bias circuitry shown in Fig. 2, it is assumed that (W/L) 10 = (W/L) 11 . This results in, both sides of the circuit, have the same current due to the current-mirror pair M 10 , M 11 . As a result, I D15 and I D13 are equal. Since V GS13 =V GS15 +I D15 .R B , then it can be shown that: Thus, the transconductance of M13 is determined by geometric ratios only and it is independent of power supply and temperature variations. In this design: and for the case: As a result, not only g m13 is stabilized, but the transconductance of all the other transistors are also stabilized since all transistor currents are derived from the same biasing network and therefore, the ratios of the currents are mainly dependent on geometry.
Compensation circuitry: This circuit is composed of the capacitor C C which controls the dominant first pole and transistor M 16 which operates as a resistor in the triode region. For this circuit it can be shown that (Roberge, 1975) the compensation can be made independent of process and temperature by simply choosing r ds16 = 2/g m7 . Table 1 shows the physical sizes of all the utilized MOS transistors, resistors and capacitors.

RESULTS
The proposed op amp chip was designed, simulated and fabricated using UMC 0.5 µm 2P2M CMOS technology. The area of the chip is about 220×120 µm. Figure 3 shows the photo the chip.
The measured variation of both the differential gain and the common-mode gain with frequency at 25°C is shown in Fig. 4. From the graph it can be seen that the open-loop gain is 84.3 dB, while the unity gain frequency is 30.5 MHz and the Common-Mode Rejection Ratio (CMRR) is 84.6 dB. This measurement shows that this chip has a high immunity for input noise. The measured variation of the power supply rejection ratio (PSRR) at two different frequencies, namely 100 Hz and 10 MHz is shown in Fig. 5. The Figure 5 shows that the PSRR + increases from 97.9 dB at 100 Hz to 107 dB at 10 MHz, while PSRR − decreases from 96.5 dB at 100 Hz to 85.5 dB at 10 MHz.  The variation of the output voltage swing is shown in Fig. 6. The curve shows that the minimum output voltage is 0.08 V and the maximum is 4.89 V which is very close to the supply voltages.
The measured Bode plot for this chip is shown in Fig. 7. From the graph it is clear that the phase margin is 60° while the gain margin is about 15 dB.
In Table 2, the measurement results for the fabricated chip are summarized and compared at both 25 and 45°C temperatures.

DISCUSSION
Utilizing P-channel MOS transistors at the input of the differential input stage increases the slew rate (by decreasing g m ) and provides good immunity against 1/f flicker noise. The utilization of the lead compensation circuit configuration (C C and transistor M 16 ) is necessary to make compensation independent of the temperature and process variations.
The dc offset voltage is reduced by simply changing the width of transistor M6 (Wu and Nabhan, 2004), taking into consideration that this can also be done by changing the widths of transistors M7, M5 and M4.
Since the utilized biasing circuitry is constant g m, then a starting circuitry is necessary. Such circuit can be simply built from an externally connected capacitor of 5 µF between VDD and ground (Gray and Meyer, 1993;Sedra and Smith, 1991).
An additional test for the circuit was carried out at two different values of R (when R = ±20% of the nominal value which is 4 KΩ). The test results reveal the goodness of the design since only the slew rate was decreased to about 20 V µS −1 when R was increased to 4.8 KΩ.

CONCLUSION
A 2.5 V CMOS op amp has been designed, simulated and fabricated using UMC 0.5 µm 2P2M CMOS technology. The measurement results indicate that that the proposed chip has a 84 dB open loop gain, a 24 V µS −1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Also, it is characterized by its high immunity to flicker noise due to the utilization of p-channel MOS transistors at the input differential stage. Moreover the utilized compensation is independent of temperature and process variations. As far as the authors are aware, this chip is the first available one in Jordan.