: Theory and Physical

: This study describes and presents the analysis for the Source-Coupled Logic (SCL) inverter as will as the effect of submicron layout parasitics. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics and the effect of noise margin. The inverter gate delay model is described and the effect of biasing current on the delay is shown. The result shows that, the delay of the SCL inverter is decreased as biasing current increase. The simulation is done based on the 0.18 µ Silterra PDK. Different layouts for SCL inverter have been investigated for its effect on output voltage swing, switching noise and the area. The results show an important effect on the SCL output signals. Post-Simulation was carried out on all proposed layouts using HSPICE and using 0.35 µ MIMOS Berhad PDK. The layout was done using Virtuous from Cadence where as the extraction done using Mentor Graphic-Caliber Interactive tool.


INTRODUCTION
In the recent era, the interesting for high-speed high-resolution mixed-signal ICs has been growing due to the diffusion of applications based on digital signal processing, including audio and video signal processing, as well as over sampled sigma-delta Analog-Digital (A/D) and Digital-Analog (D/A) conversion [1][2][3][4][5] . In these ICs, analog and digital circuits are implemented on the same silicon substrate and the resolution of the analog circuitry is severely restricted by the amount of switching noise generated by the digital blocks [6][7][8] . Actually, due to the supply current spikes during switching, logic gates generate the powersupply switching noise [3,7,[8][9][10][11] , that couples with the analog circuits through supply lines and substrate coupling, thus degrading circuit resolution. In particular, the traditional CMOS static logic generates a high amount of noise and is thus not suitable for highresolution applications. For instance, in [3] , digital and analog blocks were implemented in two different chips to obtain the required resolution, even using analog circuits with a high noise rejection and exploiting techniques such as diffusion of guard bands, keeping separate analog and digital supply lines, pads and wires [6] . As a consequence, alternative logic styles with reduced supply current spikes during switching are needed to reduce the amount of switching noise. To avoid the degradation of resolution in mixed-signal ICs, a number of approaches have been proposed at different design levels of abstraction, from technology to the system level [6,9,[12][13] . At the circuit level, the standard CMOS logic is not a feasible approach when a high resolution is required and a different logic style with reduced switching noise is required [3,6,14] . Among the possible topologies [6,12,13,[15][16][17][18][19][20][21][22][23] , one of the most successful logic styles is the Source-Coupled Logic (SCL) [6,15,17,20,[23][24][25][26] , which is based on the sourcecoupled pair of NMOS transistors and permits switching noise reduction by two orders of magnitude compared to standard CMOS logic [15,17] .
In general, compared to CMOS static logic, SCL logic style allows switching noise to be reduced by two orders of magnitude [15,17] . Since the low switching noise feature of SCL is obtained at the cost of static power dissipation, a design methodology of SCL gates is required to meet specifications, while keeping power consumption as low as possible. Moreover, design criteria to intentionally manage the power-delay tradeoff are required. SCL gates are differential. The implementation of logic functions is based on the series-gating approach, i.e., by stacking source coupled pairs [17,24,[27][28][29] . However, this approach severely limits the minimum supply voltage allowed for proper operation of stacked transistor pairs, which can be a serious drawback in current low-voltage low-power circuits. Moreover, implementation of NAND/NOR functions often requires the use of multiple cascaded gates, since each gate has a fan-in limited to 2 or 3 for practical values of the supply voltage [17,[30][31] , thus increasing the overall power consumption with respect to the case of a single gate.
In this study, the design procedure of SCL will be investigated and characterized. The SCL circuit topology and operation are explained. The SCL characterization, delay model and analytic model of noise margin is discussed and based on simulation, it is different characteristics are shown. Physical design and layout of SCL is considered for the effect of different layouts on SCL performance and amount of parasitics introduced as well as the noise effect. The simulation results of physical design are based on the post simulation using MIMOS Berhad PDK.
Topology and operation: SCL is a dual rail logic circuit that use both the variable and its complement (A, Ā) as an input pair. The output of a dual rail circuit is also a pair (E, Ē) that drives the next gate(s) in the logic cascade. However, dual rail logic interprets the difference (E-Ē) as the logic variable instead of just one or the other. When viewed at the level of Boolean algebra, the use of both the variable and it is complement is superfluous; the result is the same as that found using a single-rail circuit. Moreover, dual rail networks are more complicated to wire [32] .
The circuit schematic of SCL inverter gate, shown in Fig. 1, is made up of an NMOS source-coupled pair having transistors working in the saturation or cut off region, that approximate well the behavior of a voltagecontrolled current switch. The biasing current (I ss ) is steered to one of the two output branches and converted into a differential output voltage by two PMOS transistor working in the linear region (Active load pullup resistance) [26] . The logic function of the SCL is implemented by the logic block connected between the active load (PMOS) and the current source (I ss ). For an inverter/buffer, the logic block is the differential pair constructed by NMOS transistors M 1 and M 2 [33] . The SCL gate uses PMOS active load, but other types of load, such as physical resistor or a diodeconnected NMOS/PMOS could be used. However, resistor load is not normally chosen since large silicon area needed and its parasitic capacitance can be high. For the second type of load, the output levels will loss the threshold voltage furthermore; the MOS diode load is slower than the PMOS active load for practical bias currents [34] .

Fig. 1. SCL inverter
The operation of the SCL logic is based on the input differential pair circuit. The two inputs control the flow of current through the two branches of the differential pair. For example, if V GS (M 2 ) is higher than V GS (M 1 ), the current I D2 exceeds the current I D1 . Therefore, the output voltage V o2 begins to drop until it reach steady sate , where the current going through PMOS active load (M 4 ) matches the I D2 . In mean time V o1 is charged to V DD through M 3 .
The output voltage swing V swing is defined as voltage difference between V o1 and V o2 at steady state. The amount of current passing through the ON branch (M 2 ) controls the delay of the logic gate transition (1→0), while the PMOS active load (M 3 ) controls the charging of the output nodes (0→1 transition). Defining ∆V as the voltage drop of M 3 (M 4 ) due to the drain current equal to I ss , the logic swing of the gate, V swing equal 2∆V. To achieve best performance , all current must pass through the ON branch and the load resistance (PMOS) should be small in order to reduce the RC delay. This guarantees that the voltage is V DD -I ss .R D , where I ss is the current flowing through current source and R D is the PMOS equivalent linear resistance [33] .

SCL Characteristics:
Input-Output transfer voltage: As conversion from current-to-voltage in the SCL inverter is performed by the two PMOS transistors M 3 -M 4 , both of which have a source-gate voltage equal to V DD and a much smaller source-drain voltage (in order of hundred milivolts). Therefore, transistors M 3 -M 4 work in the triode region and can be modeled as an equivalent linear resistor R D [34] .
Using the standard BSIM3v3 MOSFET model [35] , under the static condition, PMOS transistor can be suitably approximated by an equivalent linear resistance R D given by: where R DS = (R DSW  1e-6)/W p models the source/drain parasitic resistance which depends on the empiric model parameter R DSW as well as the PMOS transistor effective channel width W p . R int is given by: This represent the intrinsic resistance of PMOS transistor in the linear region (it does not account for the parasitic drain/source resistance). In Eq. 2 the µ eff,p represents the effective hole mobility, parameter L p is the PMOS effective channel length, C ox is the oxide capacitance per area and V th,p is the threshold voltage [26] .
The output voltage V o (V i ) SCL inverter can be evaluated by substituting the equivalent resistance R D in 1.
Thus, the differential output voltage V o is equal The minimum differential input (V i ) required to fully switch the entire tail current I ss to one side is give by [36] : Which gives output transfer characteristics: Where, V i = V i1 -V i2 (Differential input). From 5, V OL = -R D I ss and V OH = R D I ss , then the logic swing is equal to [34] : From 5, that output voltage swing (V swing ) is a function of R D for fixed I ss . R D is controlled by the aspect ratio of PMOS, so for desired V swing , the aspect ratio can be varied accordingly.
To verify the theoretical analysis, the simulation was carried out on the SCL inverter gate. For evaluate the V swing , DC simulation is done by varying the aspect ratio of the PMOS with fixed I ss =10µA. Figure 2 shows the differential output voltage of SCL inverter as function of differential input (V i ) , when (V i ) is greater certain value the SCL inverter fully switch to either side and passing all I ss to that side. The value of output voltage is function of R D and it is controlled by the aspect ratio of PMOS.
The V swing /2 (I ss .R D ) must be kept low enough to ensure the NMOS transistors M 1 -M 2 are not in the triode region. In particular, when the gate voltage of an NMOS transistor is high (equal to V DD ), the drain voltage is equal to V DD-I ss .R D , the triode region can be avoided if the gate-drain voltage V GD is lower than threshold voltage by: Which imposes an upper bound to I ss .R D and hence the logic swing as given by 6 [34] .

Noise Margin (NM):
Due to the symmetrical property, the logic threshold is equal to zero (V LT = 0) and the associated small-signal voltage gain is g m,n .R D , (where g m,n is the small-signal transconductance of transistor M1-M2 with I D1,2 = I ss /2) [26] .
Since v i1 = v i2 = v o1 = v o2 = V DD -∆V/2 and I D1,2 = I ss /2, when the gate is biased around logic threshold, voltage V DS of transistor M1-M2 is equal to their V GS . Hence, the resulting expression of the voltage gain A V is [26] : The NM is equal to NM L (for Low-Logic) and similar to NM H (for High-Logic) due symmetrical property, which is defined as NM H = V OHmin -V IHmin (NM L = V ILmax -V OLmax ) where V ILmax and V IHmin are the input voltage values such that ∂vo/∂vi = -1. V OLmax and V OHmin are the corresponding output voltages (V OLmax = Vo(V IHmin ) and V OHmin = Vo(V ILmax )) [34] . By differentiating (5) for v i and setting it to -1, V IHmin results is Where A V >>1/√8 has been assumed. Approximating V OHmin to -∆V leads to the following expression of NM: Where A V >>1/√2 was assumed. The value of NM is proportional to half the logic swing [34] . Simulations were performed by setting V swing to 600 mV, I ss to 10 uA and varying the NMOS aspect ratio (dimensions in nm). The effect of A V is shown in Fig. 3, which shows how ∂vo/∂vi changes with W n . A V increases for low values of NMOS aspect ratio then asymptotically tends to a constant value as illustrated in Fig. 4. The SCL inverter gate output delay increases linearly as W n increases thus limiting us to small W n , as shown Fig. 5. applies, since the circuit is symmetrical and it's input is differential [25] . Figure 6, shows the small-signal model of the halfcircuit concept. The circuit has time constant (τ) that can be evaluated by applying the open-circuit time constant method [37] . It gives the resulting delay as 0.69τ, assuming a step input waveform and neglecting the high-frequency zero. Hence, the propagation delay τ PD,SCL of the SCL gate is given by [34] : τ PD,SCL = 0.69 * R D (C gd,n +C db,n +C gd,p +C db,n +C L ) (11) The NMOS capacitance C gd,n , in (11) is evaluated in the saturation region. Thus its value equal to the overlap capacitance C gd0 .W eff between the gate and the drain. Junction capacitances C db,n and C db,p can be linearized by modifying their value in a zero-bias condition via coefficients K j according to [39] . Capacitance C gd,p is equal to the sum of the overlap contribution C gd0 W eff,p and the intrinsic contribution associated with the channel charge of the PMOS transistors working in the linear region, C gd,p,int . In particular, we can adopt the BSIM3v3 capacitance model [36] , which express capacitance C gd,p,int as the derivative of charge flowing into drain Q D with respect to the voltage V D [25] : This derivation assumes the gate, source and bulk voltage are constant and using A bulk,max (maximum bulk charge effect) slightly greater than unity and assuming V SD << V SG -|V th |/A bulk .
To validate the delay model, the bias current was varied from 10-100 µA, the transistor aspect ratios were sized to obtain the typical value V swing = 600 mV, A V = 1.94 and the load capacitance C L was set to 0 F, 100 fF and 1 pF, respectively.  Figure 7 show the results. As expected, the delay is decreased by increasing the bias current I ss and asymptotically tends to a constant value.

SCL physical design:
As the design margins decrease steadily, the analogue problems (matching, crosstalk) rises it is affect to the circuit's performance. The dominance of parasitics has shifted from the vertical plan (towards GND) to the lateral one (cross)-coupling. The electrical parasitic extraction is the process of estimating or calculating the undesirable by product elements of the physical layout of a circuit. It is utilized to improve the model behavior of a circuit and to highlight the design imperfections and allows the designer to make the circuit more robust. The electrical parasitics are the sum of the electrical characteristics (resistance, inductance and capacitance) of any interconnects (Fig. 8) [39] . Those interconnects have an important contribution through their R and C components on the electrical circuit parameters such as delay, crosstalk or matching, especially in deep submicron technologies and that's why it becomes more important to take these effects into account during the IC simulations [40,41] .
All mentioned parasitics are dependent on the way of laying out the circuit in the IC design; the way of laying out the circuit is the amount of RC parasitic is added, so, that is affecting all performance of the circuit. In the next sections different techniques of laying SCL inverter will be applied to examine the effect of RC parasitic on the output signals by employing post-simulation with input dual opposite pulses shown in Fig. 2, the limits and constrain of all layouts are the design rules of the MIMOS 0.35u PDK.
First layout: Direct layout is applied and each transistor is laid as discrete component according to layout design rule. Whole W and L of NMOS/PMOS transistors are laid directly. The signal paths among different interconnections terminals are made directly as short as possible with minimum path width. Two metal layers are used M1 and M2 for signal paths. This layout utilizes 14 S/D interconnections. This layout is shown in the Fig. 9.
Second layout: Fingering technique is applied to divide the W of NMOS and PMOS on two transistors connected in parallel as shown in the Fig. 10. This layout utilizes 17 S/D interconnections and two layers M1 and M2. This layout utilizes more area than first one due of fingering. Third layout: Comb In this layout the NMOS and PMOS transistors are laid in comb way, which reduces the area and drain/source interconnections, also its provides interdigitized and common centroide structure as shown in Fig. 11. This layout utilizes 11 S/D interconnections. For same inputs, the result shows that the output V swing of the 2nd and 4th SCL inverter layout is greater than 1st and 3rd due of more interconnections of drain and source by using fingering which cause more parasitic resistance. The parasitic capacitance in 2nd layout is more than in 4th layout as more S/D interconnections are used, so more areas, which clear from switching noises. Even, the 3rd layout introduces more parasitic capacitance than 1st for the same reason. All layouts introduce some amount of resistance due of paths and interconnections which increase the V swing than netlist V swing , Fig. 13, shows the outputs of SCL inverter net list and it is four layouts for input pulses of 100ns/200ns. As the frequency of inputs pulses increases, the shape of output signals get distorted totally as the RC parasitic is function of signal frequency and the signal delay become superfluous Fig. 14.

CONCLUSION
The study work presents the basic theory and operation of SCL logic as well as the effect of layout on the SCL performance. The delay of inverter SCL gate is validated by Cadence-Spectre simulation using a 0.18µ Silterra PDK. Different parameters which affect the SCL logic are characterized. The SCL delay is decreased by increase of biasing current. The output voltage swing is small which reduce the dynamic power consumption. The SCL logic draws a fixed static current from the supply. The other advantages of SCL which inherited from its differential design include common mode noise rejection, insensitivity to process change and friendliness to neighboring analog circuit components.
The layouts introduce RC parasitic capacitance by signal paths and the way of transistor layout. The different ways of laying out the SCL inverter shows important effect on the performance and signal delay. The post-simulation shows that, the V swing and switching noise are affected by the layout technique; also the total area of the circuit can be reduced significantly. The outputs of four different layouts of SCL show the effect of parasitics on signal delay and output resistance. The introduced parasitics by layouts are increased by increasing of inputs signal frequency. All post-simulation was carried out by using HSPICE, where the layout is done using Virtuoso -Cadence and the extraction done by using Mentor Graphic -Caliber Interactive tool on MIMOS 0.35u PDK.