VHDL DESIGN AND HARDWARE REALIZATION OF HYBRIDARTIFICIAL INTELLIGENCE ARCHITECTURE

Evolutionary Algorithms (EA) use Genetic Algorithm (GA) in many optimization problems to efficiently compute the function value in less time. In this study the weight optimization of the Artificial Neural Network (ANN), using the Back Propagation Network (BPN), is tested and presented with GA. The combined architecture of Neuro-Genetic (Hybrid Artificial Intelligence) approach is proposed and simulated results are provided along with device Utilization, Simulation time, Timing analysis and power analysis by using very high speed integrated circuits Hardware Description Language (HDL).


INTRODUCTION
Charles Darwin proposed the "Theory of Evolution" in the year 1858. The Evolutionary Algorithms (EA) are broadly classified into three categories. They are Evolutionary Strategies (ES), Evolutionary Programming (EP) and Genetic Algorithms (GA) (Palmes et al., 2005). Ingo Rechenberg andHans-Paul Schwefel (1960s andearly 1970s) solved complex engineering problems through artificial evolution strategies using optimization method. John Holland is the initiator for the development of Genetic algorithms in 1970s (Mitchell, 1998). Further, the motivation for the development of neural network technology stemmed from the desire to develop an artificial system that could perform "intelligent" tasks similar to those performed by the human brain. In 1943 the first neuron model was developed by the McCulloch and Pitts. Afterwards Evolutionary Computation (EC) and Neural Network technology impressed the interest of many researchers (Bose, 2007). A neural network is a powerful data modeling tool that is able to capture and represent the complex input/output relation-ships (Haykin, 1999). The development of back propagation algorithm in 1986 by Rumelhart and McClelland paved the way to research and development in the field of neuro computation till now. Most of the other neural network structures represent models for "thinking" that are still being evolved in the laboratories. However, Genetic algorithms are a class of optimization procedures which are good at exploring a large and complex space in an intelligent way to find values close to the global optimum. Hence, they are well suited to the problem of training feed for-ward networks (Montana and Davis, 1989). The power and usefulness of artificial neural networks has been demonstrated in several applications including speech synthesis, diagnostic problems, medicine, business and finance, robotic control, signal processing, computer vision and many other problems that fall under the category of pattern recognition (Alsmadi et al., 2011).
The main advantage of evolutionary computation has inspired new resources for optimization problem solving, such as the optimal design of neural networks and fuzzy systems (Juang, 2004). Field Programmable Gate Array (FPGA) are becoming increasingly popular for prototyping and designing complex hardware systems. The structure of FPGA can be described as an array of blocks connected together via programmable interconnections (Blake et al., 1997;Sahin et al., 2006). The relatively low cost and easiness

AJAS
of implementation and reprogramming of FPGA's in comparison with the custom VLSI technology offer attractive features for the designer (Botros and Abdul-Arir, 1994;Ameur et al., 2012;Mahyuddin et al., 2009) Here in this study, the neuro-Genetic system is designed and simulated by using VHDL.

NEURO-GENETIC APPROACH
The traditional problem solving approach analyses the task and then derives a suitable algorithm. If successful, the result is immediately available. Neural networks can solve problems which are difficult to describe in analytical manner. But prior to usage, the network must be trained (Lange, 2005). A feed forward Back Propagation neural network is used to estimate the weights. The optimum selection of weights reduces the search-pace of the Genetic Algorithm (GA) to improve its performance (Kannaiah et al., 2011;Ditthakit and Chinnarasri, 2011). Figure 1, the evaluation function or fitness function is used to determine the fitness value of each candidate in the population. The proposed combined architecture will be helpful to solve the hardware implementation of the Hybrid AI.

Training Algorithm of BPN
It involves four steps (Sivanandam and Deepa, 2006) Step 1: Initial weight selection Step 2: Feed forward network Step 3: Error calculation Step 4: Updating of the weight and biases The parameters are x: Input training vector (x 1 ,……………x n ) t: Output target vector ∆ k : Error at output unit y k ∆ j : Error at hidden unit z j α: Learning rate v oj : Bias on hidden unit j zj: Hidden unit j w ok : Bias on output unit k y k : Output unit k Equation (1)

Procedure for Genetic Algorithm
The important parameters used in genetic algorithm are crossover rate, mutation rate, population size, selection, encoding and crossover and mutation type.
The algorithm is as follows: Step 1: Initial-Random selection of population Step 2: Select parents from population Step 3: Perform crossover on parents creating an offspring Step 4: Mutation operation for the best Individuals (offspring) Step 5: Determine the fitness Step 6: Repeat the process for the selection of the best individual and discard the worst

RESULTS
GA with BPN is tested by using the hardware unit xc3s500e-4-pq208. The simulation result, device utilization and timing summary are tabulated in Table  1 to 3 respectively. The total number of Pins in the device are 208 and used pins in the proposed design are 49 only. Net skew is the difference between the minimum and maximum routing only delays for the net. Clock skew is the difference between the minimum and maximum path delays which include logic delays. The obtained clock report is presented in Fig. 4. Here the combined architecture (Fig. 2) used the roulette wheel selection method for fitness calculations. Based on the application, different methods can be used for fitness calculations. The total memory usage is 167380 kilobytes. The Total time to complete the simulation is 6.189 ns (4.567 ns logic, 1.622 ns route) (73.8% logic, 26.2% route). Total REAL time to Xst completion: 11.00 sec and Total CPU time to Xst completion: 11.48 sec. The output of the neuro-genetic is given in Fig. 3. The selected device consumed voltage, thermal and power information's are given in the screen shots (Fig. 5-7). It is evident that the utilization of hardware and efficiency to reduce power consumption in various factors of the proposed design are achieved.

CONCLUSION
The proposed method of neuro-genetic hardware architecture design is one of the successful implementation methods of Hybrid AI in FPGA. The device utilization, clock report, power summary, voltage source information, thermal Information and power analyzers show that the proposed method is achieving the required speed and efficiency. In future the proposed method will be used for different real time applications.