CHARACTERISTIC ANALYSIS OF DUAL GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR BY MATHEMATICAL MODELING

In this study, the characteristics of DGMOSFET were obtained using mathematical modeling. The variatio ns f characteristics were analyzed with different condit ions into consideration. Different parameters behav ior is analyzed, such as Transcapacitance variation with t he gate voltage, threshold voltage variation with r espect to lateral straggle parameter and temperature, mobile charge density variation is also analyzed and also the drain characteristics of the DGMOSFET. The maximum drain current is obtained as 40 mA. The work is done usin g SPICE simulation software. The results obtained are in greater coherence with previous theoretical inv estigations.


INTRODUCTION
Researchers have been working on the performance of the devices from past two decades. DGMOSFET is one such milestone in the evolution of devices. Silicon on insulator technology is extremely attractive in terms of performance and advanced scalability. As compared to bulk silicon, the architecture of DGMOSFETs is more flexible because more parameters, such as thicknesses of film and buried oxide, substrate doping and back gate bias, can be used for optimization and scaling. It is well known that the short-channel effects are remarkably reduced in SOI films. Since bulk MOSFETs are expected to reach their limit for gate lengths below 30 nm (Chaudhry and Kumar, 2004;Brown et al., 2002), alternative architectures have been proposed to overcome their limitations. The Double-Gate (DG) transistor is considered one of the most promising devices for extremely scaled CMOS technology generations (Widiez et al., 2005).
Indeed, due to a good electrostatic control of the channel by the two gates, it is expected to provide smaller short-channel effects, near ideal sub-threshold slopes and higher drive currents when compared to single-gate transistors. Advantage of Double gate SOI MOSFET over conventional, Single Gate MOSFET can be described in terms of performance and potential for ultimate Scaling. The Peculiarity of DG-MOSFET is that the top and bottom gates are biased simultaneously to established equal surface potential VG1 = VG2, for identical gate oxides, Or VG1 = VG2 (tox1/tox2) to compensate for the difference in front and back oxide thickness (Widiez et al., 2005).

Theory
In a conventional, bulk-silicon microcircuit, the active elements are located in a thin surface layer and are isolated from the silicon body with a depletion layer of a p-n junction. The leakage current of this p-n junction exponentially increases with temperature and is responsible for several serious reliability problems. Excessive leakage currents and high power dissipation limit the operation of microcircuits at high temperatures. Parasitic n-p-n and p-n-p transistors formed in neighboring Science Publications AJAS insulating tubs can cause latch-up failures and significantly degrade the circuit performance.
Silicon-on-insulator technology employs a thin layer of silicon isolated from a silicon substrate by a relatively thick layer of silicon oxide. The SOI technology dielectrically isolates components and in conjunction with the lateral isolation, reduces various parasitic circuit capacitances and thus, eliminates the possibility of latchup failures. Figure 1 shows the typical structure of DGMOSFET. The mathematical modeling (Jazaeri et al., 2013;Smith, 2008) of the device is explained as follows.
The Gaussian profile in the channel region is modelled as: • NCD (P)-peak of gaussian profile = 1×10 20 cm −3 • The gate work fn is 4.6ev • Degenerated doping value N de -2.7×10 19 cm −3 • Parabolic potential distribution along the vertical direction: where, a(x),b(x),c(x) determined using boundary conditions continuity of electric flux at the S i -S io2 interface Ψ(x,0) = α(x): For a weak inversion operation, the 2D poisson equation, at S i -S io2 interface, considering lateral source drain profile: Ionization energy EI considering many body effects involving ionized donor e − interaction is:

AJAS
Using the potential expression of (1) and the values of a(x),b(x),c(x), the poisson can be written as i.e.,: where, natural length: The solution of (9) can be carried out by calculating its complimentary fn and the particular integral.
Calculation of PI including the Gaussian term is mathematically very complex to implement in a compact model.
We have approximated the PI by considering the absolute value of Gaussian profile at each point of the channel.
The above equation can be written as: x / x / 1e 2e f C C PI Build in potential (V bi ) can be approximately used as: The min potential point: Is calculated by equating: The threshold voltage is defined as the gate voltage when the channel τ densitives at the min potential point reach the channel doping density:

Dual Gate MOSFET
The concept of a Double-gate MOSFET is that it efficientlycontrols the channel from gates on both sides of the channelinstead of one gate in planar bulk MOSFETs. Controllingthe channel by multiple gates has its supremacy of better control over the channelinversion, so the short channel effect is reduced. Morespecifically, reducing the current leakage and eliminatingthe draininduced barrier lowering effect areexamples of superiority in double-gate MOSFETs. (Antoniadis et al., 2006;Keyes, 1986;Mohapatra et al., 2012).
The new methodologies give rise to two paths; one is the introduction of new materials into the classical single gate MOSFETs where we can develop uniaxial/biaxial strain (Widiez et al., 2005;Smith, 2008;Vaddi et al., 2012) and which improves the carrier mobility and drive current by introducing new materials in the channel region. Second is the development of non-classical Multigate MOSFETs which is very good concept for further scaling of the device dimensions (Antoniadis et al., 2006;Keyes, 1986;Dunga et al., 2006). Kumar et al. (2007) had shown the effect of strain/Ge mole fraction on the threshold voltage for a single gate MOSFET. DG-MOSFETs have substituted traditional bulk MOSFETs, which suffer from severe second-order effects, such as short channel effects that result in performance loss (Young, 1989).

RESULTS
In this section, the results obtained by the mathematical modeling and simulation of the device structure shown in Fig. 1 are presented. Figure 2 represents the typical dual gate MOSFET and its operation. Figure 3 represents the drain current variation with respect to the gate voltage and this graph represent the convention FET device characteristics, which is very encouraging. The maximum drain current value obtained in this case is 40 mA with a gate source voltage variation from 0 to 10V. Figure 4 represents the mobile charge density variation with respect to lateral direction. Figure 5 represents the threshold voltage variation with respect to the lateral straggle, a key parameter for a DGMOSFET structure characterization. Figure 6 and 7 represents the Transcapacitance variation with the gate to source voltage for different doping concentration values and Fig. 8 represents the effect of temperature on the threshold voltage of the device.

CONCLUSION
The operation of DGMOSFET brings significant advantages: Scalability, high current drive, low short channel effects, excellent transconductance. The results represents the variation of the parameters like threshold voltage, Transcapacitance under different biasing and other constraints, this would necessarily establish their effect on the performance of the device, particularly in the device characteristics. This study can be extended for different illumination conditions of DGMOSFET, which may in turn increase the performance of the device.The futurescope of this study also exist in the comparative study of various multigate devices.