An Analysis of Interleaved Boost Converter with LC Coupled Enhanced Soft Switching

An enhanced soft switching technique for an interleaved boost converter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) during OFF and ON conditions of the main switches, that can drive large loads operated in duty cycle greater than 0.5 is proposed in this study. In this topology, auxiliary circuit is composed of resonant tank which is used to decrease the voltage stress on the main switches and a coupling capacitor is added additionally with minimum resonance which in-turn increases the life of operation of the converter. In this model, faster switching and suitable impedance matching is achieved with reduction in auxiliary circuit reactance that has contributed much increase in the overall performance. Coupled inductor in the boosting stage helps higher current sharing between the switches. The overall ripple and Total harmonics distortions are reduced in this technique without sacrificing the performance and efficiency of the converter. A simulation module constructed using “MATLAB Simulink” illustrates the better results of the proposed converter.


INTRODUCTION
The boost converter is a popular choice for most power electronic systems to serve as a pre-regulator, due to advantages of simplicity and high performance (Pan et al., 2009). However, as the power rating increase, it is often required to associate converters in series or in parallel. In high-power applications, interleaving of two boost converters is very often employed to improve performance and to reduce the size (Gallo et al., 2010). Because interleaving effectively doubles the switching frequency and also partially cancels the input and output ripples, the size of the energy-storage inductors and differential-mode EMI filter in interleaved implementations can be reduced (Jang and Jovanovic, 2007). Interleaving reduces the output capacitor ripple current as a function of duty cycle. As the duty cycle approaches 0, 50 and 100% duty cycle, the sum of two diode currents approaches dc. At these points, the output capacitor only has to filter the inductor ripple current. It can be shown that by applying different duty cycles to the two phases of an interleaved boost converter according to voltage-second balance, their voltage gain will be different. The phase with larger duty cycle may have large voltage gain and operate in Continuous Inductor Current Mode (CICM), while the other will then automatically operate in Discontinuous Inductor Current Mode (DICM). Under this condition, any further additional loading current will be taken up by the phase CICM operation (Wang et al., 2008). Hence the analysis of the converter operated in duty cycle greater than 50% is an efficient approach in interleaved boost converters.

AJAS
The AC mains utility supply ideally is supposed to be cleaned and free from high voltage spikes and current harmonics in order to ensure good quality and efficient power system harmonics to electronics equipment. But in practical condition the ripples are inevitable, which needs to be minimized (Daut et al., 2006). Various ongoing research proposals are focused with some limitation as follows.
To reach the smooth soft switching, the circuits proposed require more complex auxiliary circuits which totally increase the conduction loss (Stein et al., 2002;Hsieh et al., 2009). Due to extra inductor, the auxiliary unit is complex, even the main switches are ZCS and the auxiliary switches are ZVS. The main switches are ZCS at the turn-on transition, while in turn off the switching is hard (Stein et al., 2002). A better soft switching circuit is proposed, but the converter works in discontinuous mode with duty cycle less than 50% (Yao et al., 2007). Even after analyzing with duty cycle more than 50%, the number of switching phases and switching timing is high due to increased auxiliary resonance and voltage stress to the auxiliary switch (Chen et al., 2012). The higher switching frequency may cause the higher switching losses, higher Electro-Magnetic Interference (EMI) and the lower overall efficiency. The use of soft-switching techniques in converter can contribute to reduce them (Felix and Kumar, 2012).
In this study, a soft switching technique for an interleaved boost converter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) for the main switches, which is operated in duty cycle greater than 50% with wide range of operating load, is proposed. In this topology, the voltage stress on the main switches is shared by the resonant tank composed of a resonant capacitor and inductor forming an effective auxiliary circuit. To increase the durability of the switch used, a coupling capacitor is added additionally with minimum resonance. Faster switching and suitable impedance matching is achieved with reduction in auxiliary circuit reactance which has increased the overall performance. Better current sharing between the switches is obtained by coupling the boost inductors. The overall ripple and Total harmonics distortions are reduced with higher efficiency of the converter. The forth coming sections will reveal the effectiveness of the enhanced converter.

Design and Analysis
For the case analysis, the circuit is analysed in Continuous Conduction Mode (CCM) with various load ranges having different duty cycle. The Proposed interleaved Boost Converter with LC coupled Soft Switching is shown in Fig. 1. It utilizes the interleaved boost converter topology and applies enhanced soft switching methodology where the resonant tank itself triggers the switches for extreme condition. The resonant tank is composed of Resonant Capacitor Crc and Resonant Inductor L rc which in-turn act as a control circuit for the auxiliary switch S ax , that is responsible for ZVS and ZCS function.

Principle of Operation
The circuit is operated in fundamental mode with duty cycle D which is exact symmetrical in function. The circuit is analysed with certain assumptions to simplify the circuit analysis which are listed as: • All switches and diodes are assumed to be in practical condition with an exponential decay α in the computation for theoretical analysis • Idealizing the input and output reactance • The two boost inductors are coupled • Same duty cycles (D 1 = D 2 ) for the main switches S s1 and S s2 The flow of current in initial stages through the boost inductor has an effect of interference which results in addition of ripples. Thus, for the initial input current to be clear from input ripple, a guard is introduced, which is a magnetic couple by a ferrite core which has high permittivity and hence the coupling is more effective.
Boost inductors B L1 and B L2 is energized by the magnetic flow across the inductor causing fluctuation in the input current. It is minimized by placing the iron core between the coils which looks like a transformer arrangement. Thus the flow of current is regulated by the magnetic coupling across the inductors.
The mutual inductance exerted by both the boost inductor is given by Equation 1: where, µ r and K are Permittivity of the core and coupling co-efficient respectively. According to the circuit theory, the coupled inductor can be realized with an uncoupled inductor which needs an additional inductor for coupling. There by Equation 2 and 3: L and L are considered to be leakage inductances which has major influence over the input current ripple. By regulating the coupling coefficient, the amount of ripples in the input current can be controlled. On the other hand, the output from the inductor is given by the expression which depends only on the leakage inductance Equation 4 and 5: The overall current in the converter is given by the Equation (6), which is the hypotenuses cosine function of the capacitance: The significance of the equation is that overall effectiveness of current sharing of the converter is predetermined from the inductor current. Flow of current through the two switches is calculated by the following expressions Equation 7 and 8: The overall cycle time is of the inductor output current with or without ripple and it can be expressed in the time of propagation of current in inductor, which is usually specified as a function of line frequency of input (i.e., Indian standards, 50 Hz) Equation 9: In this consideration of the switch S s1 , the total power applied to the auxiliary switch is given by the expression (10). The resistance in the parasitic (R) elements contributes for the maximum power usage in the switch Equation 10-12: The overall output current I(t p ) in the converter is calculated as the integral of inductor current. The current purely depends on the resonant circuit of the device in use.
It is an inevitable fact that, in practical conditions, it is not possible to produce the duty cycle exactly at 50%., hence the design is analysed for two different modes of operation viz duty cycle (D) lesser and greater than 50%.

Operational Analysis when Duty Cycle is Greater than 50%
In this analysis, there are 12 operational modules which comprise of a complete cycle. Here, analysis is done only on 6 modes which are related to main switch S S1 . The operating modes of the circuit for duty cycle greater than 50% is shown in Fig. 2 and 3 shows the related wave forms under same condition. Fig. 4a-f shows the active stages of the converter during operation.

Stage I [t 0 -t 1 ]
In this stage, due to the pre-excitation in duty cycle, all the switches (S s1 , S s2 , S ax ) are active and the rectifier diodes D r1 , D r2 and clamped diode D r are turned off.
Here the main switch current I s1 and I s2 are less than previous mode. The main switch S s2 achieves ZCS at time t 1 = t 0 Equation 13:

Stage II [t 1 -t 2 ]
Here, the energy stored in the resonant circuit [L rc ,C rc ] is transferred to the output load by a clamped diode D r . This happens because auxiliary switch voltage attains zero. The flow of current from resonant circuit I rc is equal to the total output current I 0 which is equal to boost inductor current I BL1 (t) Equation 15: The overall execution of stage 2 is based on the LC resonant that produces damped oscillation in LC network which is supported by an input voltage that makes the system to produce sustained output.

Stage III [t 2 -t 3 ]
At this stage, the damped diode D r is turned off. The energy stored in boost inductor BL 1 and the parasitic capacitor C s1 is transferred to resonant circuit and hence the rectifier diode D r2 is turned on. When the main switch voltage V s1 and resonant capacitor C rc increases to V 0 at t = t 3 Equation 16-18: The parasitic capacitor C ax of the auxiliary switch is given linearly by I BL2 -I rc to V 0 .

AJAS Stage IV [t 3 -t 4 ]
In this stage, at t 4 the clamped diode D r is turned ON. The energy stored is the inductor L rc is transferred to output V o through clamped diode D r and the Switch S S2 turn-on has no effect on the main switch S S1 .
In this the time, it is necessary to consider an intermediate time which is given Equation 19 and 20: So the excitation current I Lin (t n ) is given is terms of time constrain Equation 21:

Stage V [t 4 -t 5 ]
In this stage, both main and auxiliary switches are turned OFF. The stored energy in LC network is discharged to the load via D r which is a clamped diode and that will act as a bypass for the current flow. Now the input current charges the parasitic capacitance in the switches. The resonant current continues to increase to the peak value and the main switch voltage C s1 decrease to zero, because of the resonance, among elements, turns the switch S S2 to be in ON condition Equation 22 and 23: At this stage, all the voltages tend to equal. V rc (t 5 ) = V c1 (t 5 ) = V s2 (t 5 ) = V cc (t 5 ) = V Equation 24: Now at the end of this stage, the charged inductor helps the rectifier diode to turn ON.

Stage VI [t 5 -t 6 ]
When the resonant capacitor voltage V cr and the main switch voltage V s2 are equal to zero, the body diode D S2 of S S2 is turned ON. The time should be a fraction of normal operational time of stages. So in this stage one main switch S S1 achieves ZCS and other Main Switch S S2 achieves ZVS Equation 25: Boost inductor current i BL1 when switch is active in duty cycle greater than 50%, where active stages are (t 12 , t 34 , t 56 ).
Total time for switch to be in ON is T-(t 12 +t 34 +t 56 ) Equation 29 and 30:

Simulation Design and Analysis 2.5.1. Converter Specification
The switching frequency f s = 50 Hz, the output voltage V 0 = 440V and the range of output power P out are 200W-800W. The range of operating voltages 150V-220V.

Estimation of Boost Inductors and Output Capacitor
To support wide range of load a variable capacitor is used to provide impedance matching between the levels. The range of output capacitance is 200-700 µF most preferably above 400 µF. The boost inductors B L1 and B L2 are designed to operate in CCM. The design consideration of the parameters are given by:

Estimation of Resonant Capacitor and Coupling Capacitor
Resonant capacitor plays an important role in all aspects of switching, energy storage, impedance matching and load driving so the design of resonant capacitor enhances the overall performance of the converter. The total reactance of the system is the sum of reactance from capacitor and inductor which is equal to the overall energy stored in the system: where, L C 1 X and x are reactance of inductor and capacitor respectively. Consider the charge and equivalent energy charge per storage in resonant tank. The operating frequency of the tank circuit is given by 50Hz, so the calculation of resonant capacitor is obtained from (33) by substituting known values Equation 33: By simplification with the known values of maximum allowed parasitic capacitance in MOSFET switches, the coupling capacitance and resonant capacitance is given as 1.5 µF and 2.5 µF respectively.

Estimation of Switching Time
Switching time of the converter is controlled by the resonant and parasitic elements by analyzing those elements which will give necessary time constraint for soft switching.

Design of Arrival Time of ZVS Condition
When time taken by the switch S S1 to achieve ZVS, the voltage across the source to drain must be zero. The same is achieved in stage 5 for mode D>50%. The minimum time considered for the arrival of ZVS is given by.

Design of Arrival Time of ZCS Condition
Time at which the switch S S2 achieve ZCS is in stage 6 for mode D>50%. The minimum time considered for the arrival of ZCS is given by the resonant inductor current.
In stage 6 (D >50%), the calculation of ZVS arrival time is given as Equation 35 and 36: Thus, the design can give the Maximum Duty time of soft switching condition with the above constraints. All the above parameter values are tabulated in Table 1.

Parametric Analysis of the Circuit
The interleaving technique in power convertor is simulated with desired specification of ZCS and ZVS. Furthermore for better understanding, Total Harmonic Distortion (THD), the efficiency, operational range, gain, stabilizing the duty cycle and reverse recovery loss are to be calculated. The overall mathematical analysis is focused on such qualities for easier optimization of the circuit.

Current Sharing
The current sharing in parallel path is a major design problem, which is minimized by using a coupled inductor in input stage. The magnetic interference on the adjacent path couples the flow of current and so the current sharing between the parallel conductors will turn to be effective. Average current that is shared by the switches are equal i.e., Thus the current from an inductor B L1 is controlled by both the inductor, so maximum sharing of current can be easily achieved. This shows that the current flowing through the switches is equal to each other. The circuit is symmetrical and hence the expressions for the flow of current through the paths are meant to be equal. From the above, the average Current Shared by Inductors I L1 and I L1 is manipulated to be 3.5A.

Diode Conduction and Reverse Recovery Losses
The recovery current in terms of charge and recovery time enable the calculation of the loss are found to be simple Equation 43

AJAS
In switching the operation of diode for rectification of input the loss associated with the clamped diode is given as a function of change in phase angle and with the total charge recovery of the diode Equation 46: From the above calculation the total switching loss in a converter is given by Equation 49: Finally, the reverse recovery loss of overall system including 8 diodes and 3 switches is 12.96 Watts which is just 2.16% of total power.

RESULTS AND DISCUSSION
The operation of the converter under the various load from 200 to 800W with the duty cycle greater than 50% are shown below. Based on the design consideration and required conditions, the proposed interleaved boost converter with both ZVS and ZCS characteristics is built and it is shown in concerned places with proper indication. The simulated output waveforms ( Fig. 5-6) of the proposed circuit are obtained with an input voltage of 150V and the load current of ~0.6A. While verifying the output of both the switches S S1 and S S2 , it will be same, as the circuit is symmetrical. The proposed method has a designed switch with a practical decay constant (α) which is dependent factor on temperature, working life span, range of conductivity and various physical factors.  . 6. Simulation waveforms of the main switches S S1 , S S2 (a) (b) ZVS and ZCS operation while operating in duty cycle above 50% with load current 1.45A

Fig. 7. Efficiency measurement
The efficiency measurement for various loads is shown in Fig. 7, which shows the effectiveness of the proposed converter. Various parameters are tabulated in Table 2 which compares the performance of existing converters and proposed converter. The switching timing of the proposed converter indicates the fast switching transition of the circuit when compared with existing topologies. Further, the results shows that the proposed converter can be implemented with better power factor for the practical applications like Solar System, PV Panel, Grid Systems, Green Power System and Semiconductor Industries.

CONCLUSION
An enhanced soft switching technique for an interleaved boost converter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) for the main switches operated in duty cycle greater than 50% is proposed in this study. The converter can drive wide range of load with higher efficiency.
From this topology, decreased voltage stress of the main switches, faster switching, suitable impedance matching, better THD, reduced ripples, reduced reverse recovery loss and conduction loss, equal current sharing and better overall efficiency is achieved, which effectively reveal the performance of the proposed converter.