Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs

: Problem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (2 8 ) based S-Boxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The results obtained from Virtex-6 FPGA show that the proposed method runs at a clock frequency of 0.785ns, which is three times faster than S-Box based on Galois Filed GF (2 8 ). Conclusion: The reduced version of the S-Box based on prime number shows promising results as compared to Galois Field GF (2 8 ) based S-Box, which could be used in AES to increase its complexity and add more confusion.


INTRODUCTION
The National Institute of Standards and Technology (NIST) has adopted a block cipher, which was subsequently developed by Belgian researchers Vincent Rijmen and Joan Daemen and named as Rijndael cipher algorithm Advanced Encryption Standard (AES) (FIPS-197, 2001;Daemen and Rijmen, 2002). The transmission of sensitive electronic financial transactions and digital signature applications heavily rely on cryptographic algorithms. Cryptographic algorithms offer secrecy, integrity and non-reproduction of exchanged information over the fast and insecure digital communication networks. The implementation of cryptographic algorithms on the Field Programmable Gate Array (FPGA) provides a promising solution that combines with high flexibility with the speed and as well as physical security of traditional hardware Application Specific Integrated Circuits (ASICs) (Mangard et al., 2003).
The substitution box (S-Box) is a computationally intensive and requires more than 75% of the FPGA resources (Aziz and Ikram, 2007). The S-Box is a nonlinear component of the AES algorithm based on the Galois Field GF (2 8 ) provides confusion capability (Tran et al., 2008). S-Box based on Galois Field GF (2 8 ) is constructed by performing two transformations; first taking a multiplicative inverse in the Galois Field GF (2 8 ) and then applying a standard affine transformation over Galois Field GF (2 8 ). The S-Box based on residue of prime numbers (Abuelyman, and Alsehibani, 2008) adds more confusion than the S-Box based Galois Field GF (2 8 ), because it exploits most of the resources since it is required in every round (Harvey, 2000). To date, researcher (Aziz and Ikram, 2007;Henriquez et al., 2003;Zambreno et al., 2004;Badillo et al., 2006;Talwar and Rajpal, 2006;Li et al., 2007;Kundi et al., 2009;RezaeiPour and Said, 2009;Mirvaziri et al., 2009;Kundi et al., 2010) have reported S-Box based fast and efficient algorithms, but no one has look at the importance of data security, which is also very important. The acceleration of the process is also one of the prime factors and the security of the data is another. Looking at these important parameters a S-Box based on reduced Residue of Prime Numbers can be used, which results in similar table entries to S-Box based on Galois Field GF (2 8 ) (Abuelyman and Alsehibani, 2008).
The AES algorithm is an iterative algorithm and each iteration is called a round. Each round mixes the data with a round key, which is generated from the encryption key. Figure 2 presents AES algorithm structure with round operations. As shown in Fig. 2, each of the nine rounds consists of four transformations: SubBytes, ShiftRows, MixColumns and AddRoundKey with the exception of MixColumns transformation in the last round. SubBytes can be implemented either by computing the S-box, which is consists of 16 identical 256-byte substitution table or using Look-Up- Table (LUT).

MATERIALS AND METHODS
The S-Box based on Residue of Prime Numbers is a complete S-Box with 256 entries and the full details of this table is given in (Abuelyman and Alsehibani, 2008;Rais and Qasim, 2010). The Table 1 shows the reduced version of S-Box based on Residue of Prime Numbers. As it is reported in (Abuelyman and Alsehibani, 2008;Rais and Qasim, 2010) S-box based on reduced Residue of Prime Numbers produces more confusion, which is not present in Galois Field GF (2 8 ) based S-Box.

DISCUSSION
The performance of the proposed design is evaluated based on the FPGA implementation results. Table 2-3 present the FPGA implementation results of both the designs using Virtex-5 and Virtex-6 FPGA devices. Compared with the design using Galois Field GF (2 8 ), reduced Residue of Prime Numbers based S-Box operates at a maximum clock frequency of 512.821 MHz using Virtex-5 and 1273.885 MHz using Virtex-6. The proposed design utilizes only 31 occupied slices of Virtex-5 FPGA and 43 occupied slices of Virtex-6 FPGA as compared to 2 occupied slices and 1 block RAM (BRAM) used in Galois Field GF (2 8 ) based S-Box design for Virtex-5 and 1 occupied slice and 1 BRAM for Virtex-6 FPGAs.

CONCLUSION
In this study we have presented a resource efficient and much faster S-Box design based on the reduced Residue of Prime Numbers. The proposed design is implemented in Xilinx Virtex-5 and Virtex-6 FPGAs and the results are compared with that of Galois Field GF (2 8 ). The reduced version shows promising results which could be used in AES to increase its complexity and add more confusion in order to provide further resistance against algebraic attacks.

ACKNOWLEDGEMENT
The researcher acknowledges the assistance and the financial support provided by the Cornea Research Chair, College of Applied Medical Sciences, King Saud University. In particaular, I would like to thank Dr. Muhammad H. Rais for his vaulable support in this study.