Subway Train Braking System: A Fuzzy Based Hardware Approach

: Problem statement: Automated subway train-braking system require perfection, efficiency and fast response. In order to cope with this concerns, an appropriate algorithm need to be developed which need to be implemented in hardware for faster response. Approach: In this research, the FPGA realization of fuzzy based subway train braking system has been presented on an Alter FLEX10K device to provide an accurate and increased speed of convergence of the network. The fuzzy based subway train braking system is comprised of fusilier, inference, rule selector and defuzzifier modules. Sixteen rules are identified for the rule selector module. After determining the membership functions and its fuzzy variables, the Max-Min Composition method and Madman-Min implication operator are used for the inference module and the Centre of Gravity method is used for the defuzzification module. Each module is modeled individually using behavioral VHDL. The layers are then connected using structural VHDL. Two 8-bit and one 8-bit unsigned digital signals are used for input and output respectively. Six ROMs are defined in order to decrease the chances of processing and increasing the throughput of the system. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system as well. We have validated the hardware implementation of the proposed approach through comparison, verification and analysis. The design has utilized 2372 units of LC with a system frequency of 139.8MHz. Conclusion: In this research, the FPGA realization of fuzzy brake system of subway train has been successfully implemented with minimum usage of logic cells. The validation study with C model shows that the hardware model is appropriate and the hardware approach shows faster and accurate response with full automatic control.


INTRODUCTION
Fuzzy techniques are becoming an attractive approach to handle uncertain, imprecise, or unmodeled data in solving control and intelligent decision-making problems (Zadeh, 1972;Al-Odienat, 2008). This is mainly due to their inherent ability to describe a complex system by means of a simple set of intuitive and ambiguous behavioral rules. The application of fuzzy technologies into real-time control problems demands the development of efficient hardware implementations of fuzzy inference mechanisms.
In this paper, fuzzy logic utilities for synthesis of control system are discussed in the context of an application to the subway train braking system. A fuzzy based subway train braking system has the advantage that it allows the intuitive nature of accurate prediction of brake pressure to be easily modeled using the number of linguistic terms, the respective membership functions for each linguistic variable, the inference mechanism, the rules, the fuzzification and defuzzification methods (Victor and Dourado, 1997;Zachary, 2010). Due to the relative computational simplicity of fuzzy rule-based system, intelligent decision can be made in real-time, thus allowing an accurate prediction of brake pressure.
The Field-Programmable Gate Arrays (FPGA) offers a potential alternative to speed up the hardware realization (Coussy et al., 2009;. From the perspective of computer-aided design, FPGA comes with the merits of lower cost, higher density and shorter design cycle (Choong et al., 2005;Akter et al., 2008). It comprises a wide variety of building blocks. Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language . This programmability and simplicity of FPGA made it favorable for prototyping digital system. FPGA allows the users to easily and inexpensively realize their own logic networks in hardware. FPGA also allows modifying the algorithm easily and the design time frame for the hardware becomes shorter by using FPGA Ibrahimy et al., 2006).
In this study, a unified framework for FPGA realization of fuzzy based subway train braking system is designed by means of using a standard hardware description language VHDL. The use of VHDL for modeling is especially appealing since it provides a formal description of the system and allows the use of specific description styles to cover the different abstraction levels (architectural, register transfer and logic level) employed in the design (Pang et al., 2006. In the computation of method, the problem is first divided into small pieces, each can be seen as a submodule in VHDL. Following the software verification of each submodule, the synthesis is then activated. It performs the translations of hardware description language code into an equivalent netlist of digital cells. The synthesis helps integrate the design work and provides a higher feasibility to explore a far wider range of architectural alternative . The method provides a systematic approach for hardware realization, facilitating the rapid prototyping of the fuzzy based subway train braking system.

MATERIALS AND METHODS
FPGA realization of subway train braking system using fuzzy technique is introduced to implement a dedicated hardware for faster and accurate response with full automatic control. The subway train braking system, which determines the amount of brake pressure with given two inputs: distance and speed. The fuzzy based subway train braking system is comprised of four major blocks: the fuzzifier, the rule selector, the inference and the defuzzifier. Three membership functions 'distance' and 'speed' as input and 'brake' as output are chosen. For 'distance', the range of 500m with fuzzy variables of Very Close, Close, Far and Very Far are chosen.  The inference inputs the truth-values generated from the fuzzification process. The inference module performs the fuzzy composition using Max-Min Composition and Mamdani-Min implication operator (Mamdani et al., 1947;Zimmermann et al., 1985). The inference engine goes through all the rules in the rule selector, applies a composition type to evaluate the firing strength of each rule-which in turn is proportional to the truth-value of the preconditions.
The defuzzification module converts the fuzzy output set, back to a crisp number by using the Centre of Gravity method. A block diagram illustrating the major blocks of the subway train braking system is shown in Fig. 1. The system consists of two inputs: X0 and X1, each corresponding to the values of distance and speed respectively. The output of the system gives the predicted brake pressure to be applied. In VHDL modeling of the fuzzy based subway train braking system, the entity declaration provides an "external" view of a component. It defines an interface to a component and describes the properties of the components' ports.
The overall structure consists of the main entity of the fuzzy logic controller, "Train_FLC" and four components namely, "Fuzzifier", "Inference", "Rule_Selector" and "Defuzzifier". All the operations done in the system are carried out with unsigned numbers and all the components are connected to one another through the VHDL structural description.
The inputs are directly mapped into the Fuzzifier and Rule_Selector. The outputs of the Fuzzifier are mapped into the Inference. Following that, the outputs of the Inference and the Rule_Selector components are mapped into the Defuzzifier.

Fuzzifier:
The starting block, fuzzifier takes two inputs 'distance' and 'speed', which are crisp values and converts them to fuzzy values.
Each of the membership functions expressed as U mX C = + , where U is the membership function of the fuzzy variable and X is the crisp inputs with distance (X0) and speed (X1). The variable m is the gradient of the line equation while the variable C represents the intersection at the U axis (Donato and Barbieri, 1985;Alcalaa et al., 2007). The fuzzifier has one fuzzifier-entity and four ROM components labeled as 0, 1, 2 and ROM_3. It has two 8-bit input ports and four 8-bit output ports. The input ports are labeled as 0 and X1, which takes the value of distance and speed while the output ports are labeled as 1, 2, 11and MU12. These output ports are mapped into the Inference component.
Initially, the crisp values of distance and speed are normalized and passed into the fuzzifier module, where the values are rounded and converted to hexadecimal. All the hexadecimal values are printed into text files and passed into the VHDL ROM codes. The 8-bit inputs of distance and speed are translated into memory locations in the ROM, which are actually the fuzzified membership function values, mapped at different values from the universe of discourse.
Each ROM has one 8-bit input and one 8-bit output as address and data respectively. The address ports take the value of 0-X1, while the data ports maps into the output ports 1, 2, 11 and MU12 of the fuzzifier. _0 -ROM_1 consist of fuzzified values for distance while 2 and ROM_3 consist of fuzzified values for speed.

Inference:
The inference block accepts four inputs from the fuzzifier block, which are inferred using the Max-Min Composition and Mamdani-Min implication operator to produce four outputs.
It contains one Inference entity and one component outputs 0-R1, 2-R3. The inputs of inference are mapped from the outputs of fuzzifier and the outputs of the labeled as Comparator. The Inference entity consists of four 8-bit inputs, 1-MU02, 11-MU12 and four 8-bit inference are mapped into the defuzzifier as its input. The inference provides a minimum of the membership function values from the fuzzifier. The minimum value, found by mapping the inference inputs, is fed into the comparator as input.

Rule selector:
The rule selector takes two crisp inputs, distance and speed. In the rule selector module, only two fuzzy variables exist in each region of comparison. Therefore, after analyzing the membership functions of both speed and distance, it is divided into seven regions. The division of regions for input 0 and X1 is shown in Table 2.
Once all the regions are determined, each of the regions in distance is compared to the regions in speed. At each comparison, a corresponding associated rule from the fuzzy rule selector is fired. For faster inferencing and defuzzification, singleton sets are applied in the system. The output of the rule selector takes the values of the singleton values indicated by the fired rule.
The entire process for all the comparison of regions considering inputs of 0 and X1 were drawn up and tabulated in an Active Rules Lookup Table. Thus for each comparison, the rule selector looks up the table and determines the rules to be fired and its corresponding singleton values. The rule selector has one Rule_selector entity and two components. The Rule_selector entity has two 8-bit input ports and four 8-bit output ports. The input ports 0 and X1 take values of distance and speed. The output ports 0, 1, 2 and S3 are mapped into the defuzzifier. The component region functions as a region selector.
The entity Region has two 8-bit input ports, X0 and X1 and one 6-bit output port X. There are 49 region combinations to determine the rules to be fired.
The ROM_output entity has one 6-bit input port Y and four 8-bit output ports 0, 1, 2 and 3. The ROM_output contains the singleton values of S0-S3. The most significant 16 bits hold the binary values of S3 down to S2 while the 16 least significant bits hold the binary values of 1 and S0.

Deffuzifier:
The defuzzifier module takes four inputs from the inference module and four inputs from the rule selector module. The output of the defuzzifier is the brake pressure. The defuzzifier converts the fuzzy values back into the crisp values. The Centre of Gravity method was chosen for defuzzification that favors "central" values in the universe of discourse and only takes into account the area of the resultant membership function. This method of defuzzification is expressed by the equation ( ) ( ) The defuzzifier block contains one entity Defuzzifier and four components labeled as Adder8bit, Adder16bit, Multiplier and Divider. The Defuzzifier entity has eight 8-bit inputs: S0, S1, S2, S3, R0, R1, 2-R3 and one output 'brake'. The inputs S0-S3 are mapped from the rule selector, while the inputs 0-R3 are mapped from the inference unit.
An 8-bit adder, a 16-bit adder, four 8-bit multipliers and a divider are chosen to realize the Center of Gravity method. A total of four multipliers are used since there are four S inputs and four R inputs. The multiplier unit accepts two 8-bit signals and provides a 16-bit signal, which performs the multiplication of R i ×S i . The outputs of each multiplier are then added. Thus, the 16-bit output signal of the multiplier is fed into a 16-bit adder. The 16-bit adder has an output of 18-bit due to the carry bits. The output of the inference is fed into an 8-bit adder, which produces an output of 10-bits again due to the carry bits. The divider component performs the division operation by converting the divisor containing the output of the 8-bit adder to its inverse. The ROM values are then multiplied with the dividend that contains the outputs of the 16-bit adder. The multiplication produces an output of a 34-bit number. However, since the first 16-bits represent the decimal value of the number, the remaining bits are neglected. Therefore, the output would only consist of an 8-bit signal to the Brake port.

Simulation:
In order to evaluate the performance of the VHDL model of subway train braking system, a set of input values of distance and speed are fed into the model. Singleton output values from the fuzzifier and the rule selector are taken to analyze the degree of fulfillment and the brake values are taken for verification of the overall output. The input values are converted into its binary form before being entered into the test-bench of the VHDL model. The generated simulated waveform is shown in Fig. 2 and the converted binary values of hexadecimal output are tabulated in Table 3.
The same input, which is a real value, is fed into a C model in order to compare the result. The C model was set as benchmark against the VHDL model. The corresponding output is shown in Table 4.

Synthesis:
For the designated hardware realization, the VHDL code is synthesized by considering an Altera FLEX10K: EPF10K10LC84 FPGA chip on an LC84 package. The FLEX 10K family provides the density, speed and features to integrate the entire systems, including multiple 32-bit buses into a single chip. The top level RTL view and the top-level technology view are shown in Fig. 3-4 respectively.

DISCUSSION
To verify the efficiency and perfectness, we have also developed the C model of our proposed design. In the comparative analysis, the output results of the C model are compared with the output of VHDL model. The percentage of error was calculated as shown in equation (1) Using the above equation, the errors for the brake outputs are calculated and shown in Table 5.
In Table 5, it is being shown that the maximum error is indicated as 3%. Most of the large errors occur at the fuzzified outputs. This is due to the fact that the crisp values have to be converted to fuzzy values in the fuzzifier. As a result, some of the values are modified due to the variation in the slope of the membership function and thereby causes some information loss. Thus the largest errors occur in the fuzzifier kernel. The synthesis esults obtained from Quartus II showed that the whole system has taken up 2372 units of logic cells, which is about 47% utilization of the device (Altera EPF10K10LC84). Further optimization is still possible though the utilization of the logic cells are already very little. The clock frequency report showed the critical frequency is 139.8MHz. This frequency is fast enough in terms of faster response of the braking system.

CONCLUSION
The FPGA realization of fuzzy based subway train braking system has been proposed and its potentialities, as indicated by the good prediction of brake values, have been presented. By simulating and synthesizing with the values of distance and speed, the proposed approach has been successfully designed, implemented and tested. It is found that the error is almost negligible when the VHDL simulation result has been compared with the results from C model, which shows that hardware realization train braking system is appropriate. Moreover, hardware solution is faster and robust than software solution.