Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

: Problem statement: Finite Impulse Response (FIR) filters are widely used in various DSP applications. The design of digital FIR filters is a very basic problem in digital signal processing. A FIR filter with multiple operation capability is certainly very useful for any real-time filtering applications. This article presents a multipurpose FIR filter design modeled by the hardware description language VHDL for real-time filtering application. Approach: The VHDL has its concept of concurrency to cope with the parallelism of digital hardware. The novel feature is the capability of the design to accomplish up to 127variable filter order and an arbitrary filter frequency response. The coefficients are calculated by Hamming windowing technique. Basing on selection embedded in the design, the model is able to execute highpass, lowpass, bandstop and bandpass filtering operations. It is set at 8-bit signed data processing. To filter the input data in time domain, Linear Constant Coefficient Difference Equation (LCCDE) is used by the filter. Results: The design outputs are validated through simulation and compilation. The output results are also compared with the MATLAB implemented calculated output results to test the correctness that proves the effectiveness of the design. Conclusion: With the capability of filtering signal in real time mode utilizing arbitrary filter shape, the multipurpose filter proves to be versatile.


INTRODUCTION
Frequency-sensitive linear filters can be divided into two categories: Finite Impulse Response filters (FIR) and Infinite Impulse Response filters (IIR). The design of FIR digital filters is a very basic problem in digital signal processing. As such, a lot of attention for the last 30 years has been received in this field. It is widely used in various DSP applications. Few examples are signal preconditioning, video convolution functions and communications. The FIR filter is chosen for applications which require linear phase or where not producing noise inside the filter is vital. True linear phase can be achieved only in an FIR filter where the impulse response is symmetric. Filters without noise can be achieved only with FIR filters. Because FIR filters can always be designed with a sufficient number of bits in the multipliers where truncation or rounding is not required after the multiplication. In the arena of digital FIR filters designing with the constant fixedpoint binary coefficients, significant work has been done (Ma and Taylor, 1990;Lim and Liu, 1988;Dey and Oppenheim, 2008).
Ascertaining filter coefficients is the main task for designing a FIR filter. Usually window method and iterative method is applied for the determination of the coefficient. Iterative method, Ramez-Algorithm permits designing of optimal filters (Kumar et al., 2010;Mogaki et al., 2007;Parks and McClellan, 1972). Difficulty in implementation by HDL is the drawback of this method. On the contrary, it is easier to implement by the window method (Oppenhaim and Schafer, 1975).
For implementing the digital filtering algorithms, the most common approaches are special purpose digital filtering chips and Application-Specific Integrated Circuits (ASICs) for higher rates (Khoo et al., 1993;Laskowski and Samueli, 1992;Evans, 1993) or general purpose digital signal processing chips for audio applications.
The Field-Programmable Gate Arrays (FPGA) offers a potential substitute to accelerate the hardware implementation (Coussy et al., 2009;Marufuzzaman et al., 2010;Reaz et al., 2007b;Verma et al., 2009). FPGA has the merits of shorter design, higher density and lower cost cycle from the point of computer-aided design (Choong et al., 2005;Akter et al., 2008;ElGizawy et al., 2010). It comprises of a wide variety of building blocks. Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language (Reaz et al., 2004b;2005b;Iskandarani, 2010). This programmability and simplicity of FPGA made it favorable for prototyping digital system. FPGA allows the users to easily and inexpensively realize their own logic networks in hardware. FPGA also allows modifying the algorithm easily and the design time frame for the hardware becomes shorter by using FPGA Ibrahimy et al., 2006).
In this study we present a model of multipurpose FIR filter by hardware description language VHDL. The aim of the work is to get a proficient structure to ease hardware implementation to attain multi-purpose filtering with variable filter order and arbitrary frequency response and to assess the feasibility of using VHDL for prototyping and quick design. The utilization of Hardware Description Languages (HDL) is steadily increasing, as digital designs become more complex and larger (Pang et al., 2006). Previous methods like schematic capture have not been as well suited for reusing design and quick prototyping of large chip designs. Utilizing VHDL for modeling is attractive. Because, a formal description of the system is offered by VHDL. It also permits using definite description styles for covering up various abstraction levels (logic, register transfer and architectural level) used in the design 2007a). At first the problem is separated into small pieces in the computation of method. In VHDL, each can be considered as submodule. Synthesis is activated after the software verification of each submodule. It does the translations of HDL code into an equal digital cells' netlist. The synthesis facilitates to integrate the design work. It also gives a higher probability to explore far wider range of architectural substitute (Reaz et al., 2004a). This method offers a systematic approach for realization of hardware which allows quick prototyping of the multipurpose FIR filter.

MATERIALS AND METHODS
In this project, a multipurpose digital (FIR) filter is realized using VHDL. It can be modeled by utilizing LCCDE as given by Eq. 1: The FIR filter involves no feedback. As such, the LCCDE can be described by Eq. 2 as follows (Kumar et al., 2010;Mogaki et al., 2007;Parks and McClellan, 1972): The FIR filter is a generalization of a running average function as we can find from the above equation. Whenever data fluctuates, averaging is usually done and then smoothed before interpretation. An M-point averaging model method is where each value of the output sequence is the sum of M consecutive input sequence multiplied by its coefficient, b k (usually less than 1).
By using windowing technique, the multipurpose FIR filter is designed. It is the most suitable algorithm because it is the easiest way for FIR filter realization. By defining the piecewise function with discontinuities at the boundaries between bands, the frequency response can be achieved. By choosing predefine windows, the specifications of the filter can be easily found which matches filter specification. Then, the coefficients can be calculated by mathematical models.
The window selection is based on the stability and causality of all filter types, high pass, low pass, band stop and band pass for windowing algorithm. The specifications which are considered for the windows are the transition width, peak stop band attenuation and peak side lobe amplitude. A tradeoff between transition width and peak stop band attenuation remains. The transition width gets bigger as soon as the window gets higher stop band attenuation. As such, Hamming window which has a tradeoff between peak stop band and transition width attenuation is chosen.
MATLAB's fir2 function is utilized to determine the coefficient number. The interpolation point is set to 128 points and maximum order is limited upto 127 (7 bits) for VHDL realization. The frequency breakpoints and magnitude are divided into 101 sections. With the resolution of 0.01, each of them ranges from 0-1. Values are scaled up with a factor of 100 which is represented with 7 bits as VHDL is unable to function with floating point. To produce corresponding filter coefficients in real time, the filter specifications are supplied into filter model. To filter the signal, LCCDE is employed in time domain. A 256 points FFT generator is utilized to assist generation of the code to automate the design. The algorithm flow is illustrated in Fig. 1 for the filter.
The complication of multipurpose VHDL coding is in the filter coefficient calculation part. All codes are written in one file. Some codes are used again for the similar operation. The codes arrangements are illustrated in Fig. 2.
Process block is the main component for the architecture in the multipurpose FIR filter model. It handles the instruction execution flow as well as external and internal signal porting and filtering process. Like LCCDE concept used in the specific 15order filter, the coefficients in multipurpose filter are initialized by computation of the filter coefficients basing on MATLAB's fir2 function. Figure 3 shows major part of the architecture.
In the process_block, the main execution instruction flow is dependent on enable_in port. The filter stays in the idle mode when it is "00", specifications are sent to the filter when "01", filter coefficients are calculated at "10" and input data are fed for the purpose of filtering at "11". In the code below, the IF/Else condition for main process is illustrated.
If (clock = '1' and enable_in = "00" and clock' event) then (idle mode) ElsIf (clock = '1' and enable_in = "01" and clock' event) then (Obtain filter specifications) Elsif(clock = '1' and enable_in = "10" and clock' event) then (computation of filter coefficients) Elsif(clock = '1' and enable_in = "11" and clock' event) then (Filtering process) End if; Since the filter is supposed to operate in the real time, a buffer is created for receiving the input data even though the filtering process has not started. The size of the buffer is 700 elements of integer type. When the enable_in is set to "01", the filter order is pumped into the filter serially once the clock is triggered from low to high. The maximum of filter order is set to 127 or 2 7 orders. After 7 cycles, when 7 bits are gathered by the buff3, the order is converted into integer as described in the code below. Constant cosine: array91:= Array91' (1000,1000,999,999,998,996,995,993,990,988,985,982,978,974,970,966,961,956,951,946,940,934,927,921,914,906,899,891,883,875,866,857,848,839,829,819,809,799,788,777,766,755,743,731,719,707,695,682,669,656,643,629,616,602,588,574,559,545,530,515,500,485,469,454,438,423,407,391,375,358,342,326,309,292,276,259,242,225,208,191,174,156,139,122,105,87,70,52,35,17,0); The degree involves division of the filter order but only power two denominator is synthesized. Since, every fraction is divided by the filter order, the nominator and denominator are both multiplied by 128, which is of power of two. Using the Case statement, an additional nominator is used for different order so every order is divisible by 128 to emulate the division of filter order as described below. After obtaining the degree, it might vary from 0-360° but the cosine constant only ranges from 0-90°. Hence, trigonometry theorem is used so that the cosine value is obtained for the value of degree more than 90. The code to obtain the value of the Hamming window is given below. Next, the filter's frequency response is interpolated to 128 points using same algorithm obtained from fir2 function as described below. The interpolation points are then assigned to the signals before they are ported to the FOURIER_TIME_SHIFT component.

RESULTS AND DISCUSSION
To verify the performance and functionality, the multipurpose FIR filter is simulated utilizing VHDL testbench. As the stimuli to the VHDL model consists of a huge data, it is extracted from a text file. For file manipulation, the std.textio.all library is utilized. As such, the data is read line by line from the text file. Then it is fed into the model. The output of the filter is written in another text file after filtering. Together with the signal, the location of the output and input files are declared. Signals from testbench which ported to VHDL model under the test described by VHDL code are shown below: UUT: FIRFilter port map (order =>order, freq=>freq, amp=>amp, enable_in=>enable_in, clock=>clock, input=>input, output=>output ); To find out the VHDL model's performance, the output frequency response using MATLAB and VHDL simulations are analyzed and compared. The specification of an order 20, 16, 18 and 20 for Hamming window band stop, high pass, low pass and band pass filter respectively is inserted in the VHDL model for generating filter coefficients. Then the coefficients are further compared with the results generated from the MATLAB for verification. In Table 1, the specifications are given.
The mulitpurpose filter model operating frequency is 1MHz with a period of 1µ sec. Using an external clock, the frequency is pumped in the model. Effectively the square wave duty cycle is 0.5 with a 0.51µ sec period. The output results also operate with the clock at the same frequency. Changes in both input and output occur on the waveform during the transition as only the clock transition from low to high triggers the filter executions.
With 1 µ sec period, each bit of input signal is fed in the model. To get rid of misreading from the previous bit value, a delay of 0.05 µ sec in the bit stream is used. As given in Fig. 4, at the beginning of simulation, the enable_in is pumped with "01". The frequency break points and magnitude are fed to the corresponding ports for the duration of state "01". Thereafter the enable_in is changed to state "10". The calculation time for the filter coefficients at the state "10" is approximately 20 cycles as given in Fig. 5. Hence, the delay is introduced to the enable_in port before the state "11" is introduced to prompt the start of filtering process shown in Fig. 6. The coefficients generated by the multipurpose filter for band stop, high pass, low pass and band pass in the MATLAB and VHDL model are shown in Table 2. It is to be noted that the VHDL coefficients model are scaled up by 1000.
The scaled up filters' coefficients can be clearly viewed from Table 2. These are fairly close to the coefficients generated by the MATLAB. The computed values differ slightly for the approximation and truncation errors. As such, it affects the accuracy of the filter slightly when these coefficients are utilized.
The analytical comparison of the filtering is calculated by examining the signal's frequency response of VHDL and MATLAB model which is given in Fig. 7 and 8.     The filtered signal's Signal to Noise Ratio (SNR) and Mean Square Error (MSE) for the MATLAB model and the proposed multipurpose filter are compared as given in Table 3. Although the same filter specifications and algorithm are used, VHDL model has lower SNR. This happens for truncation and rounding errors in VHDL coding. Before arithmetic operations, all floating points are scaled up as VHDL does not allow floating point data type. The values are scaled up by 1000 when the filter coefficients are entered to the LCCDE. However, all the decimals places are not represented. The decimal places which exceed range are rounded to closest integer. Floating points are truncated during divide operations by division function. As such, it introduces truncation errors. Moreover, approximation errors also occur while estimating sine and cosine. This is the cause of magnitude attenuation of the filtered signal using VHDL model.

CONCLUSION
By simulating and comparing with multipurpose FIR filter MATLAB algorithm, the proposed approach of multipurpose FIR filter design using VHDL is effectively designed, realized and tested. There is significant magnitude attenuation of the filtered signal using VHDL model, which is due to scaled up the floating point. However, with the capability of filtering signal in real time mode utilizing arbitrary filter shape, the multipurpose filter proves to be versatile. For compensating filter flexibility, the accuracy of filtering is sacrificed.