A New Efficient-Silicon Area MDAC Synapse

: Using the binary representation ∑ i D i 2 i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named Arithmetic MDAC (AMDAC) is designed. It functions with a new representation based on arithmetic progressions. Using the AMS CMOS 0.35µm technology the silicon area is reduced by a factor of 40%.


INTRODUCTION
Neural network are very suitable to resolve problems where conventional resolution methods fall [1][2][3] . Synapses are the common bloc in neural network. It functions as multipliers. Their roles are to weight neural inputs by synaptic weights. Several research aims to implement synapses. Some use numeric implementation whereas others use analogue circuit. Each of these method implementations has its own advantages and drawbacks. Numeric multipliers are very suitable for applications that need high accuracy and precision results [4] . Unfortunately it occupies a considerable silicon area. Analogue synapses are efficient-silicon area and are able to operate at high frequency. However synaptic weights are badly saved in their analogue form [5][6][7][8][9][10][11][12][13] . To combine the advantages of these last implementation methods, a mixed implementation technique provides best performances [14][15][16][17][18][19][20][21][22] .
A mixed synapse named multiplier digital-toanalogue converter (MDAC) is a multiplier bloc that multiplies an analogue reference by a binary coded synaptic weight. This last is converted by a digital to analogue converter (DAC) to an analogue size, multiplied by the analogue reference and the result is routed to the output of the synapse. Current steering MDAC is the aim of this work for its capability to drive considerable charges at the output of synapses.
Several codes are used to represent the digital synaptic weights [14,15,17,[20][21][22] . The most popular are the thermometer code and the weighted binary code. The advantage of the first cited one is its low glitches. However to represent N-bits synaptic weight, 2 N-1 identical current sources are needed. To represent the same weight using binary weighted representation, N current sources, which values follow a geometric progression, are used. The use drawback of such representation is the exponential increase of the current source magnitudes. Face to this problem the design of a new MDAC synapse architecture, called AMDAC, using arithmetic progression will be presented.

Multiplication operation:
Neural network are defined as the nonlinear function of weighted sum of signals. The p-inputs of neuron, X 0 , X 1 … X p-1 shown in Fig. 1, are multiplied by the p-synaptic weights, W 0 , W 1 …, W p-1 .
The weighted sum is then forwarded to the neuron output via a nonlinear activation function S(.). Neuron output Y is then given by: From the previous equation, multiplication operation of X i W i and the addition Σ i X i W i are the two arithmetic operation performed by the neuron. The implementation of the addition is easy if outputs of the synapses are currents. It is performed when synapse outputs are connected together according to kirchhoff law (KCL). The difficulty lies in the implementation of the multiplication operation.
The MDAC synapse shown in Fig. 2a is a bloc diagram that multiplies the analog voltage V in by the binary coded synaptic weight D N-1 D N-2 …D 2 D 1 D 0 . The transfer characteristics of MDAC synapse, shown in Fig. 2b and 2c, take two forms. On one hand, when I out current is plotted according to the analog voltage V in , characteristics are straight lines which its slopes vary linearly. On the other hand, I out is a staircase shaped curves when it is plotted according to synaptic weights. From these curves integral nonlinearity error (INL) and differential nonlinearity error (DNL) are concluded. INL is an error characterization between the real staircase shaped curve and the ideal characteristic generally obtained by linear approximation of the real curve.
DNL error give a measure of how well an MDAC can generate uniform smallest analog change LSB. Thus binary synaptic inputs D N-1 D N-2 …D 2 D 1 D 0 and analog input voltage are combined by the multiplication operation: Where I out is the output current of the synapse, K is a constant, V in is the analog input voltage and C(D N-1 ,D N-2 ,…D 2 ,D 1 ,D 0 ) is to binary-to-decimal conversion law. For the weighted binary representation C(D N-1 ,D N- Binary weighted current steering MDAC MDAC circuit: The 6-bits MDAC synapse, shown in Fig. 3 is composed of: * An input circuit converting the analog input voltage V in to a proportional current I ref . * A series of scaled current mirror so that a mirror produces twice the current produced by the preceding one. Each of the stored bits D 0 to D 6 controls a switch transistor. * An output circuit inverting the sign of the current I sum issued from current mirrors. The sign circuit determines the direction of the output current, i.e. DI=0 creates a positive (excitatory) synaptic current and DI=1 sets a negative (inhibitory) synaptic current. * The total output current resulting from the scaled current mirrors is expressed by: Where I i (i=0…5) is the flowing current in the current mirror i and V i is the gate voltage controlling the current I i . V i takes only either of values V dd or zero. It is then expressed according to the binary value D i by: In the other case, when D i =1 then V i =V dd . As the size ratio of different current mirrors follow a geometric progression having the common ratio equal to 2, the current I i is done by: From the previous equation, the weighted binary to decimal conversion law is shown. Furthermore multiplication operation is shown between the analog input current and the binary to decimal conversion law. Finally, considering the sign bit DI, I out is expressed by: Simulation results of MDAC: Several simulations are carried out using 0.35µm CMOS AMS process. Figure  4 shows good linearity of the V-I converter between input analog voltage V in and the converted current I in from V in =2volt. The linearity of the V-I converter have an impact on the linear variation of the output characteristics. DC analysis show that synaptic output current versus analog input voltage, illustrated in Fig.  5a, follows a linear variation law for each synaptic weight. Linear variation of the slopes is depicted in Fig.  5b. The MDAC output current versus 6-bit synaptic weight is illustrated in Fig. 6. 127   { } 0.4µm, 0.8µm, 1.6µm, 3.2µm, 6.4µm, 12.8µm (9) The common ratio of the last geometric progression is equal to 2. To handle the transition of a weighted MDAC state to the following, an increase with the two's power of manufacturing grid is enough. Furthermore an arithmetic progression can limit the exponential increase of the geometric progression terms. Its common difference (CD) is equal to two's power of manufacturing grid. Let choose the common difference equal to 0.1µm and the first terms equal to 0.7µm. the eight arithmetic terms are: 0.7µm, 0.8µm, 0.9µm, 1.0µm, The Fig. 8 shows the circuit of AMDAC. The V-I converter and the current inverter of the AMDAC are the same that the ones presented in Fig. 3. The scaled mirror sizes follow the arithmetic progression terms of the series-10. Obviously the number representation is not the weighted binary code. A new binary representation based on arithmetic progression named binary arithmetic representation and noted A2 must be established. To represent the first state, 0.7µm-current mirror width is activated. Thus the first number representation is: 2 10 00000001 1 A = (11) Where, the 1| 10 and 00000001| A2 are respectively the notations of the decimal value of one and its A2 binary representation. In this last the only one valued bit is at the least significant bit.
The following states are generated by adding each time the common difference CD equal to 0.1µm. This corresponds to shifting the one valued bit to the more significant bits: The last value, 8| 10 , corresponds to the activation of the current mirror having the width equal to 1.4µm. The next value must activate a current mirror width equal to 1.5µm. This last size can be obtained by the activation of the two current mirrors sized W=0.7µm and W=0.8µm. consequently A2 representation of the decimal value 9| 10 is: 2 10 00000011 9 A = (13) Higher decimal values are also obtained by shifting one valued bits from the less significant bits towards more significant bits. Table 1 shows the complete eightbit representation. 71 states are noted. A2 representation is redundant because a decimal value can be represented by several A2 binary codes. For example 00011100| A2 and 00101010| A2 activate the same total current mirror width. In fact, the mirrors widths activated by the code 00011100| A2 are 0.9µm, 1µm and 1.1µm. the total width is then equal to 3µm. the same width can be obtained by the activation of 0.8µm, 1µm and 1.2µm current mirrors. The only forbidden A2 code is 11111111.
Because the first term in the arithmetic series 0.7, 0.8, 0.9…1.4 is not equal to the common difference, a correction bloc must be placed in the circuit represented in Fig. 8 to substrate the equivalent of 0.6µm current mirror width. The I sum current is expressed by: Where, I C is the correction current. For the same length transistor of the scaled mirror, the i th mirrored current I i is then equal to: Where, W 0 and CD are respectively the common difference and the first term of the arithmetic progression and they are equal to CD=0.1µm and W 0 =0.7µm. substituting equation 5, 15 in 14 and considering the sign bit DI the current I sum is expressed by: The previous equation is a multiplication between the analog current I 0 /7 and 9-signed-bit A2 representation.
Simulation results of AMDAC: Simulations AMDAC are done in the same conditions as the weighted MDAC simulations. Figure 9a illustrates linear variations of I out versus the analog voltage V in . Figure 9b shows the  Layout and comparative analysis: Using AMS 0.35µm CMOS process, layouts of 127-state MDAC and 143-state AMDAC are shown in Fig. 12. While the resolution of the latter is higher, its silicon area is lower. Area of AMDAC synapse is 589µm 2 versus MDAC synapse area equal to 909µm 2 . Table 2 summarizes the characteristics of the 7-signed-bit MDAC and the 9-signed-bit AMDAC synapses. AMDAC synapse has the lowest silicon area for better precision. For the same INL error, the DNL error of MDAC synapse is higher than AMDAC synapse.

CONCLUSION
In the present work we designed a new multiplier digitalto analog converter based on arithmetic progression called AMDAC. It functions with a new binary representation. We have demonstrated a gain in silicon area by almost of 40% for better resolution compared to classical MDAC.