TY  - JOUR
AU  - Neelakantan, P. N. 
AU  - Jeyakumar, A. E. 
PY  - 2006
TI  - Single Stuck-At Fault Diagnosing Circuit of Reed-Muller Canonical Exclusive-Or Sum of Product Boolean Expressions 
JF  - Journal of Computer Science
VL  - 2
IS  - 7
DO  - 10.3844/jcssp.2006.595.599
UR  - https://thescipub.com/abstract/jcssp.2006.595.599
AB  - A testable design with a universal test set for single stuck-at zero and stuck-at one faults of Reed-Muller canonical form of Exclusive-OR sum of product logic expressions is proposed. The test circuit detects almost all the single stuck-at faults and needs only simple modifications for variations in the circuit under test. The number of test vectors is also quite small compared with the classical method. The factor of un-identifiability is discussed and a new quantification parameter for the fault diagnosis has also been introduced. Results of Matlab simulations for a few logic functions are included.