TY  - JOUR
AU  - Benmohammed, M. 
AU  - Merniz, S. 
PY  - 2005
TI  - VHDL Specification Methodology from High-level Specification
JF  - Journal of Computer Science
VL  - 1
IS  - 2
DO  - 10.3844/jcssp.2005.270.275
UR  - https://thescipub.com/abstract/jcssp.2005.270.275
AB  - Design complexity has been increasing exponentially this last decade. In order to cope with such an
increase and to keep up designers' productivity, higher level specifications were required. Moreover new
synthesis systems, starting with a high level specification, have been developed in order to automate and
speed up processor design. This study presents a VHDL specification methodology aimed to extend structured
design methodologies to the behavioral level. The goal is to develop VHDL modeling strategies in order to
master the design and analysis of large and complex systems. Structured design methodologies are combined
with a high-level synthesis system, a VHDL based behavioral synthesis tool, in order to allow hierarchical
design and component re-use.